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Searched refs:dst_offset (Results 1 – 25 of 53) sorted by relevance

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/drivers/staging/media/atomisp/pci/isp/kernels/sdis/sdis_2/
Dia_css_sdis2.host.c210 unsigned int src_offset = 0, dst_offset = 0; in ia_css_translate_dvs2_statistics() local
246 memcpy(host_stats->hor_prod.odd_real + dst_offset, in ia_css_translate_dvs2_statistics()
248 memcpy(host_stats->hor_prod.odd_imag + dst_offset, in ia_css_translate_dvs2_statistics()
250 memcpy(host_stats->hor_prod.even_real + dst_offset, in ia_css_translate_dvs2_statistics()
252 memcpy(host_stats->hor_prod.even_imag + dst_offset, in ia_css_translate_dvs2_statistics()
256 memcpy(host_stats->ver_prod.odd_real + dst_offset, in ia_css_translate_dvs2_statistics()
258 memcpy(host_stats->ver_prod.odd_imag + dst_offset, in ia_css_translate_dvs2_statistics()
260 memcpy(host_stats->ver_prod.even_real + dst_offset, in ia_css_translate_dvs2_statistics()
262 memcpy(host_stats->ver_prod.even_imag + dst_offset, in ia_css_translate_dvs2_statistics()
266 dst_offset += host_stats->grid.aligned_width; in ia_css_translate_dvs2_statistics()
/drivers/gpu/drm/nouveau/
Dnouveau_bo90b5.c39 u64 dst_offset = mem->vma[1].addr; in nvc0_bo_move_copy() local
53 0x0314, upper_32_bits(dst_offset), in nvc0_bo_move_copy()
54 0x0318, lower_32_bits(dst_offset), in nvc0_bo_move_copy()
63 dst_offset += (PAGE_SIZE * line_count); in nvc0_bo_move_copy()
Dnouveau_bo85b5.c46 u64 dst_offset = mem->vma[1].addr; in nva3_bo_move_copy() local
60 0x0314, upper_32_bits(dst_offset), in nva3_bo_move_copy()
61 0x0318, lower_32_bits(dst_offset), in nva3_bo_move_copy()
70 dst_offset += (PAGE_SIZE * line_count); in nva3_bo_move_copy()
Dnouveau_bo9039.c44 u64 dst_offset = mem->vma[1].addr; in nvc0_bo_move_m2mf() local
57 NVVAL(NV9039, OFFSET_OUT_UPPER, VALUE, upper_32_bits(dst_offset)), in nvc0_bo_move_m2mf()
59 OFFSET_OUT, lower_32_bits(dst_offset)); in nvc0_bo_move_m2mf()
80 dst_offset += (PAGE_SIZE * line_count); in nvc0_bo_move_m2mf()
Dnouveau_bo5039.c46 u64 dst_offset = mem->vma[1].addr; in nv50_bo_move_m2mf() local
110 NVVAL(NV5039, OFFSET_OUT_UPPER, VALUE, upper_32_bits(dst_offset))); in nv50_bo_move_m2mf()
113 OFFSET_OUT, lower_32_bits(dst_offset), in nv50_bo_move_m2mf()
130 dst_offset += amount; in nv50_bo_move_m2mf()
Dnouveau_bo0039.c54 u32 dst_offset = new_reg->start << PAGE_SHIFT; in nv04_bo_move_m2mf() local
74 OFFSET_OUT, dst_offset, in nv04_bo_move_m2mf()
90 dst_offset += (PAGE_SIZE * line_count); in nv04_bo_move_m2mf()
/drivers/gpu/drm/radeon/
Drv770_dma.c43 uint64_t src_offset, uint64_t dst_offset, in rv770_copy_dma() argument
75 radeon_ring_write(ring, dst_offset & 0xfffffffc); in rv770_copy_dma()
77 radeon_ring_write(ring, upper_32_bits(dst_offset) & 0xff); in rv770_copy_dma()
80 dst_offset += cur_size_in_dw * 4; in rv770_copy_dma()
Devergreen_dma.c109 uint64_t dst_offset, in evergreen_copy_dma() argument
141 radeon_ring_write(ring, dst_offset & 0xfffffffc); in evergreen_copy_dma()
143 radeon_ring_write(ring, upper_32_bits(dst_offset) & 0xff); in evergreen_copy_dma()
146 dst_offset += cur_size_in_dw * 4; in evergreen_copy_dma()
Devergreen_cs.c2804 u64 src_offset, dst_offset, dst2_offset; in evergreen_dma_cs_parse() local
2829 dst_offset = radeon_get_ib_value(p, idx+1); in evergreen_dma_cs_parse()
2830 dst_offset <<= 8; in evergreen_dma_cs_parse()
2837 dst_offset = radeon_get_ib_value(p, idx+1); in evergreen_dma_cs_parse()
2838 dst_offset |= ((u64)(radeon_get_ib_value(p, idx+2) & 0xff)) << 32; in evergreen_dma_cs_parse()
2848 if ((dst_offset + (count * 4)) > radeon_bo_size(dst_reloc->robj)) { in evergreen_dma_cs_parse()
2850 dst_offset, radeon_bo_size(dst_reloc->robj)); in evergreen_dma_cs_parse()
2871 dst_offset = radeon_get_ib_value(p, idx+1); in evergreen_dma_cs_parse()
2872 dst_offset |= ((u64)(radeon_get_ib_value(p, idx+3) & 0xff)) << 32; in evergreen_dma_cs_parse()
2878 if ((dst_offset + (count * 4)) > radeon_bo_size(dst_reloc->robj)) { in evergreen_dma_cs_parse()
[all …]
Dsi_dma.c232 uint64_t src_offset, uint64_t dst_offset, in si_copy_dma() argument
264 radeon_ring_write(ring, lower_32_bits(dst_offset)); in si_copy_dma()
266 radeon_ring_write(ring, upper_32_bits(dst_offset) & 0xff); in si_copy_dma()
269 dst_offset += cur_size_in_bytes; in si_copy_dma()
Dr600_cs.c2381 u64 src_offset, dst_offset; in r600_dma_cs_parse() local
2404 dst_offset = radeon_get_ib_value(p, idx+1); in r600_dma_cs_parse()
2405 dst_offset <<= 8; in r600_dma_cs_parse()
2410 dst_offset = radeon_get_ib_value(p, idx+1); in r600_dma_cs_parse()
2411 dst_offset |= ((u64)(radeon_get_ib_value(p, idx+2) & 0xff)) << 32; in r600_dma_cs_parse()
2417 if ((dst_offset + (count * 4)) > radeon_bo_size(dst_reloc->robj)) { in r600_dma_cs_parse()
2419 dst_offset + (count * 4), radeon_bo_size(dst_reloc->robj)); in r600_dma_cs_parse()
2443 dst_offset = radeon_get_ib_value(p, idx+5); in r600_dma_cs_parse()
2444 dst_offset |= ((u64)(radeon_get_ib_value(p, idx+6) & 0xff)) << 32; in r600_dma_cs_parse()
2454 dst_offset = radeon_get_ib_value(p, idx+1); in r600_dma_cs_parse()
[all …]
Dr600_dma.c445 uint64_t src_offset, uint64_t dst_offset, in r600_copy_dma() argument
477 radeon_ring_write(ring, dst_offset & 0xfffffffc); in r600_copy_dma()
479 radeon_ring_write(ring, (((upper_32_bits(dst_offset) & 0xff) << 16) | in r600_copy_dma()
482 dst_offset += cur_size_in_dw * 4; in r600_copy_dma()
Dradeon_asic.h87 uint64_t dst_offset,
158 uint64_t dst_offset,
348 uint64_t src_offset, uint64_t dst_offset,
352 uint64_t src_offset, uint64_t dst_offset,
474 uint64_t src_offset, uint64_t dst_offset,
548 uint64_t src_offset, uint64_t dst_offset,
726 uint64_t src_offset, uint64_t dst_offset,
797 uint64_t src_offset, uint64_t dst_offset,
801 uint64_t src_offset, uint64_t dst_offset,
/drivers/gpu/drm/vmwgfx/
Dvmwgfx_blit.c358 u32 dst_offset, in vmw_bo_cpu_blit_line() argument
366 u32 dst_page = dst_offset >> PAGE_SHIFT; in vmw_bo_cpu_blit_line()
368 u32 dst_page_offset = dst_offset & ~PAGE_MASK; in vmw_bo_cpu_blit_line()
416 dst_offset += copy_size; in vmw_bo_cpu_blit_line()
447 u32 dst_offset, u32 dst_stride, in vmw_bo_cpu_blit() argument
457 u32 j, initial_line = dst_offset / dst_stride; in vmw_bo_cpu_blit()
493 diff->line_offset = dst_offset % dst_stride; in vmw_bo_cpu_blit()
494 ret = vmw_bo_cpu_blit_line(&d, dst_offset, src_offset, w); in vmw_bo_cpu_blit()
498 dst_offset += dst_stride; in vmw_bo_cpu_blit()
/drivers/gpu/drm/qxl/
Dqxl_ioctl.c76 uint32_t dst_offset; member
91 reloc_page = qxl_bo_kmap_atomic_page(qdev, info->dst_bo, info->dst_offset & PAGE_MASK); in apply_reloc()
92 *(uint64_t *)(reloc_page + (info->dst_offset & ~PAGE_MASK)) = qxl_bo_physical_address(qdev, in apply_reloc()
107 reloc_page = qxl_bo_kmap_atomic_page(qdev, info->dst_bo, info->dst_offset & PAGE_MASK); in apply_surf_reloc()
108 *(uint32_t *)(reloc_page + (info->dst_offset & ~PAGE_MASK)) = id; in apply_surf_reloc()
231 reloc_info[i].dst_offset = reloc.dst_offset; in qxl_process_single_command()
234 reloc_info[i].dst_offset = reloc.dst_offset + release->release_offset; in qxl_process_single_command()
/drivers/gpu/drm/tiny/
Dgm12u320.c250 int block, dst_offset, len, remain, ret, x1, x2, y1, y2; in gm12u320_copy_fb_to_blocks() local
289 dst_offset = (y1 * GM12U320_REAL_WIDTH + x1) * 3; in gm12u320_copy_fb_to_blocks()
290 block = dst_offset / DATA_BLOCK_CONTENT_SIZE; in gm12u320_copy_fb_to_blocks()
291 dst_offset %= DATA_BLOCK_CONTENT_SIZE; in gm12u320_copy_fb_to_blocks()
293 if ((dst_offset + len) > DATA_BLOCK_CONTENT_SIZE) { in gm12u320_copy_fb_to_blocks()
294 remain = dst_offset + len - DATA_BLOCK_CONTENT_SIZE; in gm12u320_copy_fb_to_blocks()
295 len = DATA_BLOCK_CONTENT_SIZE - dst_offset; in gm12u320_copy_fb_to_blocks()
298 dst_offset += DATA_BLOCK_HEADER_SIZE; in gm12u320_copy_fb_to_blocks()
302 gm12u320->data_buf[block] + dst_offset, in gm12u320_copy_fb_to_blocks()
307 dst_offset = DATA_BLOCK_HEADER_SIZE; in gm12u320_copy_fb_to_blocks()
[all …]
/drivers/gpu/drm/i915/gem/
Di915_gem_object_blt.c246 u64 src_offset, dst_offset; in intel_emit_vma_copy_blt() local
287 dst_offset = dst->node.start; in intel_emit_vma_copy_blt()
299 *cmd++ = lower_32_bits(dst_offset); in intel_emit_vma_copy_blt()
300 *cmd++ = upper_32_bits(dst_offset); in intel_emit_vma_copy_blt()
310 *cmd++ = lower_32_bits(dst_offset); in intel_emit_vma_copy_blt()
311 *cmd++ = upper_32_bits(dst_offset); in intel_emit_vma_copy_blt()
320 *cmd++ = dst_offset; in intel_emit_vma_copy_blt()
329 dst_offset += size; in intel_emit_vma_copy_blt()
/drivers/media/platform/rockchip/rga/
Drga-hw.c176 struct rga_addr_offset *dst_offset; in rga_cmd_set_trans_info() local
325 dst_offset = rga_lookup_draw_pos(&offsets, src_info.data.rot_mode, in rga_cmd_set_trans_info()
343 dst_offset->y_off; in rga_cmd_set_trans_info()
345 dst_offset->u_off; in rga_cmd_set_trans_info()
347 dst_offset->v_off; in rga_cmd_set_trans_info()
/drivers/gpu/drm/amd/amdgpu/
Damdgpu_sdma.h90 uint64_t dst_offset,
106 uint64_t dst_offset,
Dsi_dma.c778 uint64_t dst_offset, in si_dma_emit_copy_buffer() argument
784 ib->ptr[ib->length_dw++] = lower_32_bits(dst_offset); in si_dma_emit_copy_buffer()
786 ib->ptr[ib->length_dw++] = upper_32_bits(dst_offset) & 0xff; in si_dma_emit_copy_buffer()
802 uint64_t dst_offset, in si_dma_emit_fill_buffer() argument
807 ib->ptr[ib->length_dw++] = lower_32_bits(dst_offset); in si_dma_emit_fill_buffer()
809 ib->ptr[ib->length_dw++] = upper_32_bits(dst_offset) << 16; in si_dma_emit_fill_buffer()
Dsdma_v2_4.c1202 uint64_t dst_offset, in sdma_v2_4_emit_copy_buffer() argument
1212 ib->ptr[ib->length_dw++] = lower_32_bits(dst_offset); in sdma_v2_4_emit_copy_buffer()
1213 ib->ptr[ib->length_dw++] = upper_32_bits(dst_offset); in sdma_v2_4_emit_copy_buffer()
1228 uint64_t dst_offset, in sdma_v2_4_emit_fill_buffer() argument
1232 ib->ptr[ib->length_dw++] = lower_32_bits(dst_offset); in sdma_v2_4_emit_fill_buffer()
1233 ib->ptr[ib->length_dw++] = upper_32_bits(dst_offset); in sdma_v2_4_emit_fill_buffer()
/drivers/crypto/ccp/
Dccp-dmaengine.c368 unsigned int dst_offset, dst_len; in ccp_create_desc() local
389 dst_offset = 0; in ccp_create_desc()
416 dst_offset = 0; in ccp_create_desc()
435 ccp_pt->dst_dma = sg_dma_address(dst_sg) + dst_offset; in ccp_create_desc()
454 dst_offset += len; in ccp_create_desc()
/drivers/gpu/drm/gma500/
Daccel_2d.c161 uint32_t src_format, uint32_t dst_offset, in psb_accel_2d_copy() argument
199 *buf++ = dst_offset; in psb_accel_2d_copy()
/drivers/net/ethernet/mellanox/mlxsw/
Dspectrum_acl_ctcam.c29 u16 src_offset, u16 dst_offset, u16 size) in mlxsw_sp_acl_ctcam_region_move() argument
35 region->tcam_region_info, dst_offset, size); in mlxsw_sp_acl_ctcam_region_move()
/drivers/gpu/drm/i915/gt/uc/
Dintel_uc_fw.c442 static int uc_fw_xfer(struct intel_uc_fw *uc_fw, u32 dst_offset, u32 dma_flags) in uc_fw_xfer() argument
462 intel_uncore_write_fw(uncore, DMA_ADDR_1_LOW, dst_offset); in uc_fw_xfer()
501 int intel_uc_fw_upload(struct intel_uc_fw *uc_fw, u32 dst_offset, u32 dma_flags) in intel_uc_fw_upload() argument
518 err = uc_fw_xfer(uc_fw, dst_offset, dma_flags); in intel_uc_fw_upload()

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