| /drivers/media/platform/ti-vpe/ |
| D | sc.c | 62 unsigned int dst_w) in sc_set_hs_coeffs() argument
70 if (dst_w > src_w) { in sc_set_hs_coeffs()
73 if ((dst_w << 1) < src_w) in sc_set_hs_coeffs()
74 dst_w <<= 1; /* first level decimation */ in sc_set_hs_coeffs()
75 if ((dst_w << 1) < src_w) in sc_set_hs_coeffs()
76 dst_w <<= 1; /* second level decimation */ in sc_set_hs_coeffs()
78 if (dst_w == src_w) { in sc_set_hs_coeffs()
81 sixteenths = (dst_w << 4) / src_w; in sc_set_hs_coeffs()
149 unsigned int dst_w, unsigned int dst_h) in sc_config_scaler() argument
178 if (src_w == dst_w && src_h == dst_h) { in sc_config_scaler()
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| D | sc.h | 200 unsigned int dst_w);
205 unsigned int dst_w, unsigned int dst_h);
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| D | vpe.c | 865 unsigned int dst_w = d_q_data->c_rect.width; in set_srcdst_params() local
912 sc_set_hs_coeffs(ctx->dev->sc, ctx->sc_coeff_h.addr, src_w, dst_w); in set_srcdst_params()
917 src_w, src_h, dst_w, dst_h); in set_srcdst_params()
2111 unsigned int dst_w = d_q_data->c_rect.width; in check_srcdst_sizes() local
2114 if (src_w == dst_w && src_h == dst_h) in check_srcdst_sizes()
2120 dst_w <= SC_MAX_PIXEL_WIDTH) in check_srcdst_sizes()
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| /drivers/media/pci/ivtv/ |
| D | ivtv-yuv.c | 224 f->tru_w, f->src_w, f->dst_w, f->src_x, f->dst_x); in ivtv_yuv_handle_horizontal()
230 reg_2834 = f->dst_w; in ivtv_yuv_handle_horizontal()
246 if ((f->tru_x - f->pan_x > -1) && (f->tru_x - f->pan_x <= 40) && (f->dst_w >= 680)) in ivtv_yuv_handle_horizontal()
248 else if ((f->tru_x - f->pan_x < 0) && (f->tru_x - f->pan_x >= -20) && (f->dst_w >= 660)) in ivtv_yuv_handle_horizontal()
251 if (f->dst_w >= f->src_w) in ivtv_yuv_handle_horizontal()
257 if (f->dst_w < f->src_w) in ivtv_yuv_handle_horizontal()
263 reg_2870_offset = (f->src_x * ((f->dst_w << 21) / f->src_w)) >> 19; in ivtv_yuv_handle_horizontal()
265 if (f->dst_w >= f->src_w) { in ivtv_yuv_handle_horizontal()
267 master_width = (f->src_w * 0x00200000) / (f->dst_w); in ivtv_yuv_handle_horizontal()
268 if (master_width * f->dst_w != f->src_w * 0x00200000) in ivtv_yuv_handle_horizontal()
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| /drivers/gpu/drm/zte/ |
| D | zx_plane.c | 148 u32 src_w, u32 src_h, u32 dst_w, u32 dst_h) in zx_vl_rsz_setup() argument
157 zx_writel(rsz + RSZ_DEST_CFG, RSZ_VER(dst_h - 1) | RSZ_HOR(dst_w - 1)); in zx_vl_rsz_setup()
173 zx_writel(rsz + RSZ_VL_LUMA_HOR, rsz_step_value(src_w, dst_w)); in zx_vl_rsz_setup()
175 zx_writel(rsz + RSZ_VL_CHROMA_HOR, rsz_step_value(src_chroma_w, dst_w)); in zx_vl_rsz_setup()
195 u32 dst_x, dst_y, dst_w, dst_h; in zx_vl_plane_atomic_update() local
212 dst_w = drm_rect_width(dst); in zx_vl_plane_atomic_update()
234 GL_POS_X(dst_x + dst_w) | GL_POS_Y(dst_y + dst_h)); in zx_vl_plane_atomic_update()
249 zx_vl_rsz_setup(zplane, format, src_w, src_h, dst_w, dst_h); in zx_vl_plane_atomic_update()
339 u32 dst_w, u32 dst_h) in zx_gl_rsz_setup() argument
344 zx_writel(rsz + RSZ_DEST_CFG, RSZ_VER(dst_h - 1) | RSZ_HOR(dst_w - 1)); in zx_gl_rsz_setup()
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| /drivers/gpu/drm/sti/ |
| D | sti_hqvdp.c | 480 int src_w, src_h, dst_w, dst_h; in hqvdp_dbg_dump_cmd() local
519 dst_w = c->hvsrc.output_picture_size & 0x0000FFFF; in hqvdp_dbg_dump_cmd()
521 seq_printf(s, "\t%dx%d", dst_w, dst_h); in hqvdp_dbg_dump_cmd()
534 if (dst_w > src_w) in hqvdp_dbg_dump_cmd()
535 seq_printf(s, " %d/1", dst_w / src_w); in hqvdp_dbg_dump_cmd()
537 seq_printf(s, " 1/%d", src_w / dst_w); in hqvdp_dbg_dump_cmd()
735 int dst_w, int dst_h) in sti_hqvdp_check_hw_scaling() argument
741 lfw /= max(src_w, dst_w) * mode->clock / 1000; in sti_hqvdp_check_hw_scaling()
1028 int dst_x, dst_y, dst_w, dst_h; in sti_hqvdp_atomic_check() local
1039 dst_w = clamp_val(state->crtc_w, 0, mode->hdisplay - dst_x); in sti_hqvdp_atomic_check()
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| D | sti_vid.c | 146 int dst_w = clamp_val(state->crtc_w, 0, mode->hdisplay - dst_x); in sti_vid_commit() local
153 dst_w = ALIGN(dst_w, 2); in sti_vid_commit()
164 xds = sti_vtg_get_pixel_number(*mode, dst_x + dst_w - 1); in sti_vid_commit()
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| D | sti_gdp.c | 627 int dst_x, dst_y, dst_w, dst_h; in sti_gdp_atomic_check() local
640 dst_w = clamp_val(state->crtc_w, 0, mode->hdisplay - dst_x); in sti_gdp_atomic_check()
691 dst_w, dst_h, dst_x, dst_y, in sti_gdp_atomic_check()
706 int dst_x, dst_y, dst_w, dst_h; in sti_gdp_atomic_update() local
749 dst_w = clamp_val(state->crtc_w, 0, mode->hdisplay - dst_x); in sti_gdp_atomic_update()
785 dst_w = sti_gdp_get_dst(gdp->dev, dst_w, src_w); in sti_gdp_atomic_update()
790 xds = sti_vtg_get_pixel_number(*mode, dst_x + dst_w - 1); in sti_gdp_atomic_update()
795 src_w = dst_w; in sti_gdp_atomic_update()
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| D | sti_cursor.c | 192 int dst_x, dst_y, dst_w, dst_h; in sti_cursor_atomic_check() local
203 dst_w = clamp_val(state->crtc_w, 0, mode->crtc_hdisplay - dst_x); in sti_cursor_atomic_check()
249 DRM_DEBUG_KMS("(%dx%d)@(%d,%d)\n", dst_w, dst_h, dst_x, dst_y); in sti_cursor_atomic_check()
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| /drivers/media/platform/rockchip/rga/ |
| D | rga-hw.c | 166 unsigned int src_h, src_w, src_x, src_y, dst_h, dst_w, dst_x, dst_y; in rga_cmd_set_trans_info() local
185 dst_w = ctx->out.crop.width; in rga_cmd_set_trans_info()
262 if (dst_w == src_h) in rga_cmd_set_trans_info()
268 scale_dst_h = dst_w; in rga_cmd_set_trans_info()
271 scale_dst_w = dst_w; in rga_cmd_set_trans_info()
313 dst_act_info.data.act_width = dst_w - 1; in rga_cmd_set_trans_info()
324 offsets = rga_get_addr_offset(&ctx->out, dst_x, dst_y, dst_w, dst_h); in rga_cmd_set_trans_info()
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| /drivers/gpu/drm/sun4i/ |
| D | sun8i_ui_layer.c | 80 u32 src_w, src_h, dst_w, dst_h; in sun8i_ui_layer_update_coord() local
93 dst_w = drm_rect_width(&state->dst); in sun8i_ui_layer_update_coord()
100 outsize = SUN8I_MIXER_SIZE(dst_w, dst_h); in sun8i_ui_layer_update_coord()
107 dst_w, dst_h); in sun8i_ui_layer_update_coord()
151 sun8i_ui_scaler_setup(mixer, channel, src_w, src_h, dst_w, in sun8i_ui_layer_update_coord()
162 DRM_DEBUG_DRIVER("Layer destination size W: %d H: %d\n", dst_w, dst_h); in sun8i_ui_layer_update_coord()
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| D | sun8i_vi_layer.c | 75 u32 src_w, src_h, dst_w, dst_h; in sun8i_vi_layer_update_coord() local
91 dst_w = drm_rect_width(&state->dst); in sun8i_vi_layer_update_coord()
117 outsize = SUN8I_MIXER_SIZE(dst_w, dst_h); in sun8i_vi_layer_update_coord()
150 do_div(ability, mode->vdisplay * fps * max(src_w, dst_w)); in sun8i_vi_layer_update_coord()
171 hscale = (src_w << 16) / dst_w; in sun8i_vi_layer_update_coord()
174 sun8i_vi_scaler_setup(mixer, channel, src_w, src_h, dst_w, in sun8i_vi_layer_update_coord()
203 DRM_DEBUG_DRIVER("Layer destination size W: %d H: %d\n", dst_w, dst_h); in sun8i_vi_layer_update_coord()
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| D | sun8i_ui_scaler.c | 149 u32 src_w, u32 src_h, u32 dst_w, u32 dst_h, in sun8i_ui_scaler_setup() argument
167 outsize = SUN8I_UI_SCALER_SIZE(dst_w, dst_h); in sun8i_ui_scaler_setup()
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| D | sun8i_vi_scaler.c | 927 u32 src_w, u32 src_h, u32 dst_w, u32 dst_h, in sun8i_vi_scaler_setup() argument
943 outsize = SUN8I_VI_SCALER_SIZE(dst_w, dst_h); in sun8i_vi_scaler_setup()
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| D | sun8i_ui_scaler.h | 40 u32 src_w, u32 src_h, u32 dst_w, u32 dst_h,
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| D | sun8i_vi_scaler.h | 74 u32 src_w, u32 src_h, u32 dst_w, u32 dst_h,
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| /drivers/gpu/drm/meson/ |
| D | meson_plane.c | 142 int src_w, src_h, dst_w, dst_h; in meson_plane_atomic_update() local
260 dst_w = state->crtc_w; in meson_plane_atomic_update()
276 hf_phase_step = ((src_w << 18) / dst_w) << 6; in meson_plane_atomic_update()
287 if (src_h != dst_h || src_w != dst_w) { in meson_plane_atomic_update()
326 if (src_w != dst_w) { in meson_plane_atomic_update()
357 priv->viu.osb_blend0_size = dst_h << 16 | dst_w; in meson_plane_atomic_update()
358 priv->viu.osb_blend1_size = dst_h << 16 | dst_w; in meson_plane_atomic_update()
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| /drivers/gpu/drm/i915/display/ |
| D | intel_atomic_plane.c | 139 unsigned int src_w, src_h, dst_w, dst_h; in intel_plane_pixel_rate() local
144 dst_w = drm_rect_width(&plane_state->uapi.dst); in intel_plane_pixel_rate()
148 dst_w = min(src_w, dst_w); in intel_plane_pixel_rate()
152 dst_w * dst_h); in intel_plane_pixel_rate()
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| /drivers/gpu/drm/ |
| D | drm_rect.c | 174 int dst_w = drm_rect_width(dst); in drm_rect_calc_hscale() local
175 int hscale = drm_calc_scale(src_w, dst_w); in drm_rect_calc_hscale()
177 if (hscale < 0 || dst_w == 0) in drm_rect_calc_hscale()
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| /drivers/gpu/drm/imx/dcss/ |
| D | dcss-plane.c | 273 u32 src_w, src_h, dst_w, dst_h; in dcss_plane_atomic_update() local
298 dst_w = drm_rect_width(&dst); in dcss_plane_atomic_update()
321 dst_w, dst_h, in dcss_plane_atomic_update()
325 dst.x1, dst.y1, dst_w, dst_h); in dcss_plane_atomic_update()
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| /drivers/media/platform/sti/bdisp/ |
| D | bdisp-hw.c | 630 u32 src_w, src_h, dst_w, dst_h; in bdisp_hw_get_hv_inc() local
634 dst_w = ctx->dst.crop.width; in bdisp_hw_get_hv_inc()
637 if (bdisp_hw_get_inc(src_w, dst_w, h_inc) || in bdisp_hw_get_hv_inc()
641 src_w, src_h, dst_w, dst_h); in bdisp_hw_get_hv_inc()
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| /drivers/gpu/drm/rockchip/ |
| D | rockchip_drm_vop.c | 356 uint32_t src_w, uint32_t src_h, uint32_t dst_w, in scl_vop_cal_scl_fac() argument
373 if (dst_w > 3840) { in scl_vop_cal_scl_fac()
380 scl_cal_scale2(src_w, dst_w)); in scl_vop_cal_scl_fac()
385 scl_cal_scale2(cbcr_src_w, dst_w)); in scl_vop_cal_scl_fac()
392 yrgb_hor_scl_mode = scl_get_scl_mode(src_w, dst_w); in scl_vop_cal_scl_fac()
396 cbcr_hor_scl_mode = scl_get_scl_mode(cbcr_src_w, dst_w); in scl_vop_cal_scl_fac()
399 lb_mode = scl_vop_cal_lb_mode(dst_w, true); in scl_vop_cal_scl_fac()
404 lb_mode = scl_vop_cal_lb_mode(dst_w, false); in scl_vop_cal_scl_fac()
426 val = scl_vop_cal_scale(yrgb_hor_scl_mode, src_w, dst_w, in scl_vop_cal_scl_fac()
443 dst_w, true, 0, NULL); in scl_vop_cal_scl_fac()
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| /drivers/gpu/drm/exynos/ |
| D | exynos_drm_gsc.c | 748 u32 src_w, src_h, dst_w, dst_h; in gsc_set_prescaler() local
755 dst_w = dst->h; in gsc_set_prescaler()
758 dst_w = dst->w; in gsc_set_prescaler()
762 ret = gsc_get_ratio_shift(ctx, src_w, dst_w, &sc->pre_hratio); in gsc_set_prescaler()
777 sc->main_hratio = (src_w << 16) / dst_w; in gsc_set_prescaler()
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| D | exynos_drm_fimc.c | 746 u32 src_w, src_h, dst_w, dst_h; in fimc_set_prescaler() local
758 dst_w = dst->h; in fimc_set_prescaler()
761 dst_w = dst->w; in fimc_set_prescaler()
766 hfactor = fls(src_w / dst_w / 2); in fimc_set_prescaler()
785 sc->hratio = (src_w << 14) / (dst_w << hfactor); in fimc_set_prescaler()
787 sc->up_h = (dst_w >= src_w) ? true : false; in fimc_set_prescaler()
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| /drivers/gpu/drm/msm/disp/dpu1/ |
| D | dpu_plane.c | 527 uint32_t src_w, uint32_t src_h, uint32_t dst_w, uint32_t dst_h, in _dpu_plane_setup_scaler3() argument
538 mult_frac((1 << PHASE_STEP_SHIFT), src_w, dst_w); in _dpu_plane_setup_scaler3()
581 && (src_w == dst_w)) in _dpu_plane_setup_scaler3()
584 scale_cfg->dst_width = dst_w; in _dpu_plane_setup_scaler3()
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