| /drivers/crypto/hisilicon/hpre/ |
| D | hpre_crypto.c | 303 err = (le32_to_cpu(sqe->dw0) >> HPRE_SQE_ALG_BITS) & in hpre_alg_res_post_hf()
306 done = (le32_to_cpu(sqe->dw0) >> HPRE_SQE_DONE_SHIFT) & in hpre_alg_res_post_hf()
477 msg->dw0 |= cpu_to_le32(0x1 << HPRE_SQE_DONE_SHIFT); in hpre_msg_request_set()
540 msg->dw0 = cpu_to_le32(le32_to_cpu(msg->dw0) | HPRE_ALG_DH_G2); in hpre_dh_compute_value()
542 msg->dw0 = cpu_to_le32(le32_to_cpu(msg->dw0) | HPRE_ALG_DH); in hpre_dh_compute_value()
741 msg->dw0 |= cpu_to_le32(HPRE_ALG_NC_NCRT); in hpre_rsa_enc()
791 msg->dw0 = cpu_to_le32(le32_to_cpu(msg->dw0) | in hpre_rsa_dec()
795 msg->dw0 = cpu_to_le32(le32_to_cpu(msg->dw0) | in hpre_rsa_dec()
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| D | hpre.h | 79 __le32 dw0; member
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| /drivers/scsi/hisi_sas/ |
| D | hisi_sas_v3_hw.c | 436 u32 dw0; member
446 __le32 dw0; member
1154 prot->dw0 |= T10_INSRT_EN_MSK; in fill_prot_v3_hw()
1158 prot->dw0 |= (T10_RMV_EN_MSK | T10_CHK_EN_MSK); in fill_prot_v3_hw()
1163 prot->dw0 |= T10_CHK_EN_MSK; in fill_prot_v3_hw()
1168 prot->dw0 |= T10_INSRT_EN_MSK; in fill_prot_v3_hw()
1172 prot->dw0 |= (T10_RMV_EN_MSK | T10_CHK_EN_MSK); in fill_prot_v3_hw()
1176 prot->dw0 |= T10_CHK_EN_MSK; in fill_prot_v3_hw()
1189 prot->dw0 |= (0x1 << USR_DATA_BLOCK_SZ_OFF); in fill_prot_v3_hw()
1192 prot->dw0 |= (0x2 << USR_DATA_BLOCK_SZ_OFF); in fill_prot_v3_hw()
[all …]
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| D | hisi_sas_v2_hw.c | 388 __le32 dw0; member
1715 hdr->dw0 = cpu_to_le32((port->id << CMD_HDR_PORT_OFF) | in prep_smp_v2_hw()
1750 hdr->dw0 = cpu_to_le32((1 << CMD_HDR_RESP_REPORT_OFF) | in prep_ssp_v2_hw()
2033 u32 dw0 = le32_to_cpu(complete_hdr->dw0); in slot_err_v2_hw() local
2318 if (dw0 & CMPLT_HDR_RSPNS_XFRD_MSK) in slot_err_v2_hw()
2342 u32 dw0; in slot_complete_v2_hw() local
2367 dw0 = le32_to_cpu(complete_hdr->dw0); in slot_complete_v2_hw()
2368 switch ((dw0 & CMPLT_HDR_ABORT_STAT_MSK) >> in slot_complete_v2_hw()
2394 if ((dw0 & CMPLT_HDR_ERX_MSK) && (!(dw0 & CMPLT_HDR_RSPNS_XFRD_MSK))) { in slot_complete_v2_hw()
2395 u32 err_phase = (dw0 & CMPLT_HDR_ERR_PHASE_MSK) in slot_complete_v2_hw()
[all …]
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| D | hisi_sas.h | 504 __le32 dw0; member
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| D | hisi_sas_v1_hw.c | 932 hdr->dw0 = cpu_to_le32((port->id << CMD_HDR_PORT_OFF) | in prep_smp_v1_hw()
967 hdr->dw0 = cpu_to_le32((1 << CMD_HDR_RESP_REPORT_OFF) | in prep_ssp_v1_hw()
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| /drivers/net/wireless/mediatek/mt76/ |
| D | mt76x02_usb_core.c | 142 u32 tbtt, dw0, dw1; in mt76x02u_restart_pre_tbtt_timer() local
149 dw0 = mt76_rr(dev, MT_TSF_TIMER_DW0); in mt76x02u_restart_pre_tbtt_timer()
151 tsf = (u64)dw0 << 32 | dw1; in mt76x02u_restart_pre_tbtt_timer()
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| /drivers/usb/mtu3/ |
| D | mtu3_trace.h | 181 __field(u32, dw0)
189 __entry->dw0 = le32_to_cpu(gpd->dw0_info);
196 __entry->dw0, __entry->dw1,
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| /drivers/pci/pcie/ |
| D | dpc.c | 190 u32 status, mask, sev, syserr, exc, dw0, dw1, dw2, dw3, log, prefix; in dpc_process_rp_pio_error() local
217 &dw0); in dpc_process_rp_pio_error()
225 dw0, dw1, dw2, dw3); in dpc_process_rp_pio_error()
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| D | aer.c | 672 t->dw0, t->dw1, t->dw2, t->dw3); in __print_tlp_header()
1087 aer + PCI_ERR_HEADER_LOG, &info->tlp.dw0); in aer_get_device_error_info()
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| /drivers/usb/isp1760/ |
| D | isp1760-hcd.c | 54 __dw dw0; member
294 mem_writes8(base, ptd_offset + slot*sizeof(*ptd) + sizeof(ptd->dw0), in ptd_write()
299 mem_writes8(base, ptd_offset + slot*sizeof(*ptd), &ptd->dw0, in ptd_write()
300 sizeof(ptd->dw0)); in ptd_write()
550 ptd->dw0 = DW0_VALID_BIT; in create_ptd_atl()
551 ptd->dw0 |= TO_DW0_LENGTH(qtd->length); in create_ptd_atl()
552 ptd->dw0 |= TO_DW0_MAXPACKET(maxpacket); in create_ptd_atl()
553 ptd->dw0 |= TO_DW0_ENDPOINT(usb_pipeendpoint(qtd->urb->pipe)); in create_ptd_atl()
583 ptd->dw0 |= TO_DW0_MULTI(multi); in create_ptd_atl()
1149 ptd.dw0 |= DW0_VALID_BIT; in handle_done_ptds()
[all …]
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| /drivers/net/ethernet/huawei/hinic/ |
| D | hinic_debugfs.c | 115 ret = funcfg_table_elem->dw0.bs.valid; in hinic_dbg_get_func_table()
118 ret = funcfg_table_elem->dw0.bs.nic_rx_mode; in hinic_dbg_get_func_table()
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| D | hinic_debugfs.h | 42 } dw0; member
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| /drivers/dma/ |
| D | hisi_dma.c | 57 __le32 dw0; member
289 sqe->dw0 = cpu_to_le32(FIELD_PREP(OPCODE_MASK, OPCODE_M2M)); in hisi_dma_start_transfer()
290 sqe->dw0 |= cpu_to_le32(LOCAL_IRQ_EN); in hisi_dma_start_transfer()
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| /drivers/crypto/ccp/ |
| D | ccp-dev.h | 621 struct dword0 dw0; member
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| D | ccp-dev-v5.c | 156 #define CCP5_CMD_DW0(p) ((p)->dw0)
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| /drivers/pci/ |
| D | pci.c | 3142 u32 dw0, bei, base, max_offset; in pci_ea_read() local
3146 pci_read_config_dword(dev, ent_offset, &dw0); in pci_ea_read()
3150 ent_size = ((dw0 & PCI_EA_ES) + 1) << 2; in pci_ea_read()
3152 if (!(dw0 & PCI_EA_ENABLE)) /* Entry not enabled */ in pci_ea_read()
3155 bei = (dw0 & PCI_EA_BEI) >> 4; in pci_ea_read()
3156 prop = (dw0 & PCI_EA_PP) >> 8; in pci_ea_read()
3163 prop = (dw0 & PCI_EA_SP) >> 16; in pci_ea_read()
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| /drivers/crypto/hisilicon/ |
| D | qm.c | 77 #define QM_EQE_PHASE(eqe) ((le32_to_cpu((eqe)->dw0) >> 16) & 0x1)
80 #define QM_AEQE_PHASE(aeqe) ((le32_to_cpu((aeqe)->dw0) >> 16) & 0x1)
246 __le32 dw0; member
250 __le32 dw0; member
604 u16 cqn = le32_to_cpu(eqe->dw0) & QM_EQE_CQN_MASK; in qm_to_hisi_qp()
714 type = le32_to_cpu(aeqe->dw0) >> QM_AEQE_TYPE_SHIFT; in qm_aeq_irq()
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| /drivers/firmware/efi/ |
| D | cper.c | 417 aer->header_log.dw0, aer->header_log.dw1, in cper_print_pcie()
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| /drivers/net/ethernet/intel/ixgbe/ |
| D | ixgbe_main.c | 11252 u32 dw0, dw1, dw2, dw3; in ixgbe_io_error_detected() local
11271 dw0 = ixgbe_read_pci_cfg_dword(hw, pos + PCI_ERR_HEADER_LOG); in ixgbe_io_error_detected()
11291 dw0, dw1, dw2, dw3); in ixgbe_io_error_detected()
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