| /drivers/gpu/drm/i915/gem/selftests/ |
| D | mock_context.c | 29 INIT_LIST_HEAD(&ctx->stale.engines); in mock_context()
37 RCU_INIT_POINTER(ctx->engines, e); in mock_context()
107 struct i915_gem_engines *engines; in live_context_for_engine() local
111 engines = alloc_engines(1); in live_context_for_engine()
112 if (!engines) in live_context_for_engine()
117 __free_engines(engines, 0); in live_context_for_engine()
123 __free_engines(engines, 0); in live_context_for_engine()
128 engines->engines[0] = ce; in live_context_for_engine()
129 engines->num_engines = 1; in live_context_for_engine()
133 engines = rcu_replace_pointer(ctx->engines, engines, 1); in live_context_for_engine()
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| /drivers/gpu/drm/i915/gem/ |
| D | i915_gem_context.c | 238 if (!e->engines[count]) in __free_engines()
241 intel_context_put(e->engines[count]); in __free_engines()
253 struct i915_gem_engines *engines = in free_engines_rcu() local
256 i915_sw_fence_fini(&engines->fence); in free_engines_rcu()
257 free_engines(engines); in free_engines_rcu()
263 struct i915_gem_engines *engines = in engines_notify() local
264 container_of(fence, typeof(*engines), fence); in engines_notify()
268 if (!list_empty(&engines->link)) { in engines_notify()
269 struct i915_gem_context *ctx = engines->ctx; in engines_notify()
273 list_del(&engines->link); in engines_notify()
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| D | i915_gem_context.h | 173 return rcu_dereference_protected(ctx->engines, in i915_gem_context_engines()
198 struct i915_gem_engines *e = rcu_dereference(ctx->engines); in i915_gem_context_get_engine()
201 else if (likely(idx < e->num_engines && e->engines[idx])) in i915_gem_context_get_engine()
202 ce = intel_context_get(e->engines[idx]); in i915_gem_context_get_engine()
212 struct i915_gem_engines *engines) in i915_gem_engines_iter_init() argument
214 it->engines = engines; in i915_gem_engines_iter_init()
221 #define for_each_gem_engine(ce, engines, it) \ argument
222 for (i915_gem_engines_iter_init(&(it), (engines)); \
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| D | i915_gem_context_types.h | 41 struct intel_context *engines[]; member
46 const struct i915_gem_engines *engines; member
83 struct i915_gem_engines __rcu *engines; member
186 struct list_head engines; member
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| /drivers/gpu/drm/i915/gt/ |
| D | selftest_rc6.c | 155 struct intel_engine_cs *engine, **engines; in randomised_engines() local
165 engines = kmalloc_array(n, sizeof(*engines), GFP_KERNEL); in randomised_engines()
166 if (!engines) in randomised_engines()
171 engines[n++] = engine; in randomised_engines()
173 i915_prandom_shuffle(engines, sizeof(*engines), n, prng); in randomised_engines()
176 return engines; in randomised_engines()
182 struct intel_engine_cs **engines; in live_rc6_ctx_wa() local
191 engines = randomised_engines(gt, &prng, &count); in live_rc6_ctx_wa()
192 if (!engines) in live_rc6_ctx_wa()
196 struct intel_engine_cs *engine = engines[n]; in live_rc6_ctx_wa()
[all …]
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| D | intel_engine_user.c | 78 struct list_head *engines) in sort_engines() argument
86 list_add((struct list_head *)&engine->uabi_node, engines); in sort_engines()
88 list_sort(NULL, engines, engine_cmp); in sort_engines()
192 LIST_HEAD(engines); in intel_engines_driver_register()
194 sort_engines(i915, &engines); in intel_engines_driver_register()
198 list_for_each_safe(it, next, &engines) { in intel_engines_driver_register()
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| D | debugfs_engines.c | 27 DEFINE_GT_DEBUGFS_ATTRIBUTE(engines);
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| /drivers/crypto/marvell/cesa/ |
| D | cesa.c | 377 struct mv_cesa_engine *engine = &cesa->engines[idx]; in mv_cesa_get_sram()
422 struct mv_cesa_engine *engine = &cesa->engines[idx]; in mv_cesa_put_sram()
439 struct mv_cesa_engine *engines; in mv_cesa_probe() local
470 cesa->engines = devm_kcalloc(dev, caps->nengines, sizeof(*engines), in mv_cesa_probe()
472 if (!cesa->engines) in mv_cesa_probe()
490 struct mv_cesa_engine *engine = &cesa->engines[i]; in mv_cesa_probe()
574 clk_disable_unprepare(cesa->engines[i].zclk); in mv_cesa_probe()
575 clk_disable_unprepare(cesa->engines[i].clk); in mv_cesa_probe()
577 if (cesa->engines[i].irq > 0) in mv_cesa_probe()
578 irq_set_affinity_hint(cesa->engines[i].irq, NULL); in mv_cesa_probe()
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| /drivers/gpu/drm/omapdrm/ |
| D | omap_dmm_tiler.c | 297 if (dmm->engines[i].async) in omap_dmm_irq_handler()
298 release_engine(&dmm->engines[i]); in omap_dmm_irq_handler()
300 complete(&dmm->engines[i].compl); in omap_dmm_irq_handler()
758 kfree(omap_dmm->engines); in omap_dmm_remove()
897 omap_dmm->engines = kcalloc(omap_dmm->num_engines, in omap_dmm_probe()
898 sizeof(*omap_dmm->engines), GFP_KERNEL); in omap_dmm_probe()
899 if (!omap_dmm->engines) { in omap_dmm_probe()
905 omap_dmm->engines[i].id = i; in omap_dmm_probe()
906 omap_dmm->engines[i].dmm = omap_dmm; in omap_dmm_probe()
907 omap_dmm->engines[i].refill_va = omap_dmm->refill_va + in omap_dmm_probe()
[all …]
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| D | omap_dmm_priv.h | 175 struct refill_engine *engines; member
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| /drivers/gpu/drm/nouveau/nvif/ |
| D | fifo.c | 62 device->runlist[i].engines = a->v.runlist[i].data; in nvif_fifo_runlists()
93 if (device->runlist[i].engines & a.v.engine.data) in nvif_fifo_runlist()
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| /drivers/dma/idxd/ |
| D | device.c | 520 iowrite64(group->grpcfg.engines, idxd->reg_base + grpcfg_offset); in idxd_group_config_write()
652 int i, engines = 0; in idxd_engines_setup() local
658 group->grpcfg.engines = 0; in idxd_engines_setup()
662 eng = &idxd->engines[i]; in idxd_engines_setup()
668 group->grpcfg.engines |= BIT(eng->id); in idxd_engines_setup()
669 engines++; in idxd_engines_setup()
672 if (!engines) in idxd_engines_setup()
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| D | init.c | 167 idxd->engines = devm_kcalloc(dev, idxd->max_engines, in idxd_setup_internals()
169 if (!idxd->engines) in idxd_setup_internals()
187 idxd->engines[i].idxd = idxd; in idxd_setup_internals()
188 idxd->engines[i].id = i; in idxd_setup_internals()
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| /drivers/gpu/drm/i915/selftests/ |
| D | i915_request.c | 2788 } *engines; in perf_parallel_engines() local
2791 engines = kcalloc(nengines, sizeof(*engines), GFP_KERNEL); in perf_parallel_engines()
2792 if (!engines) in perf_parallel_engines()
2813 memset(&engines[idx].p, 0, sizeof(engines[idx].p)); in perf_parallel_engines()
2814 engines[idx].p.engine = engine; in perf_parallel_engines()
2816 engines[idx].tsk = kthread_run(*fn, &engines[idx].p, in perf_parallel_engines()
2818 if (IS_ERR(engines[idx].tsk)) { in perf_parallel_engines()
2819 err = PTR_ERR(engines[idx].tsk); in perf_parallel_engines()
2823 get_task_struct(engines[idx++].tsk); in perf_parallel_engines()
2832 if (IS_ERR(engines[idx].tsk)) in perf_parallel_engines()
[all …]
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| D | intel_memory_region.c | 382 struct i915_gem_engines *engines; in igt_gpu_write() local
425 engines = i915_gem_context_lock_engines(ctx); in igt_gpu_write()
430 ce = engines->engines[order[i] % engines->num_engines]; in igt_gpu_write()
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| /drivers/gpu/drm/nouveau/nvkm/engine/fifo/ |
| D | chan.c | 208 u64 mask = chan->engines; in nvkm_fifo_chan_child_get()
355 u64 hvmm, u64 push, u64 engines, int bar, u32 base, in nvkm_fifo_chan_ctor() argument
368 chan->engines = engines; in nvkm_fifo_chan_ctor()
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| D | chan.h | 25 u64 engines, int bar, u32 base, u32 user,
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| /drivers/gpu/drm/amd/display/dc/dce80/ |
| D | dce80_resource.c | 832 if (pool->base.engines[i] != NULL) in dce80_resource_destruct()
833 dce110_engine_destroy(&pool->base.engines[i]); in dce80_resource_destruct()
1087 pool->base.engines[i] = dce80_aux_engine_create(ctx, i); in dce80_construct()
1088 if (pool->base.engines[i] == NULL) { in dce80_construct()
1285 pool->base.engines[i] = dce80_aux_engine_create(ctx, i); in dce81_construct()
1286 if (pool->base.engines[i] == NULL) { in dce81_construct()
1479 pool->base.engines[i] = dce80_aux_engine_create(ctx, i); in dce83_construct()
1480 if (pool->base.engines[i] == NULL) { in dce83_construct()
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| /drivers/gpu/drm/amd/display/dc/dce60/ |
| D | dce60_resource.c | 827 if (pool->base.engines[i] != NULL) in dce60_resource_destruct()
828 dce110_engine_destroy(&pool->base.engines[i]); in dce60_resource_destruct()
1078 pool->base.engines[i] = dce60_aux_engine_create(ctx, i); in dce60_construct()
1079 if (pool->base.engines[i] == NULL) { in dce60_construct()
1276 pool->base.engines[i] = dce60_aux_engine_create(ctx, i); in dce61_construct()
1277 if (pool->base.engines[i] == NULL) { in dce61_construct()
1470 pool->base.engines[i] = dce60_aux_engine_create(ctx, i); in dce64_construct()
1471 if (pool->base.engines[i] == NULL) { in dce64_construct()
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| /drivers/hsi/ |
| D | Kconfig | 10 application engines and cellular modems.
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| /drivers/leds/ |
| D | leds-lp5523.c | 394 enum lp55xx_engine_mode mode = chip->engines[nr - 1].mode; in show_engine_mode()
416 struct lp55xx_engine *engine = &chip->engines[nr - 1]; in store_engine_mode()
486 lp5523_mux_to_array(chip->engines[nr - 1].led_mux, mux); in show_engine_leds()
496 struct lp55xx_engine *engine = &chip->engines[nr - 1]; in lp5523_load_mux()
528 struct lp55xx_engine *engine = &chip->engines[nr - 1]; in store_engine_leds()
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| /drivers/gpu/drm/nouveau/include/nvif/ |
| D | device.h | 14 u64 engines; member
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| /drivers/gpu/drm/nouveau/include/nvkm/engine/ |
| D | fifo.h | 20 u64 engines; member
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| /drivers/gpu/drm/i915/ |
| D | Kconfig.profile | 31 The driver sends a periodic heartbeat down all active engines to
57 certain platforms and certain engines which will be reflected in the
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| /drivers/infiniband/hw/hns/ |
| D | Kconfig | 20 Hip07 SoC. These RoCE engines are platform devices.
|