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Searched refs:field_name (Results 1 – 25 of 120) sorted by relevance

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/drivers/gpu/drm/amd/display/dc/gpio/dcn21/
Dhw_factory_dcn21.c60 #define SF_HPD(reg_name, field_name, post_fix)\ argument
61 .field_name = HPD0_ ## reg_name ## __ ## field_name ## post_fix
67 #define SF(reg_name, field_name, post_fix)\ argument
68 .field_name = reg_name ## __ ## field_name ## post_fix
99 #define SF_DDC(reg_name, field_name, post_fix)\ argument
100 .field_name = reg_name ## __ ## field_name ## post_fix
139 #define SF_GENERIC(reg_name, field_name, post_fix)\ argument
140 .field_name = reg_name ## __ ## field_name ## post_fix
/drivers/gpu/drm/amd/display/dc/gpio/dcn30/
Dhw_factory_dcn30.c70 #define SF_HPD(reg_name, field_name, post_fix)\ argument
71 .field_name = HPD0_ ## reg_name ## __ ## field_name ## post_fix
77 #define SF(reg_name, field_name, post_fix)\ argument
78 .field_name = reg_name ## __ ## field_name ## post_fix
110 #define SF_DDC(reg_name, field_name, post_fix)\ argument
111 .field_name = reg_name ## __ ## field_name ## post_fix
164 #define SF_GENERIC(reg_name, field_name, post_fix)\ argument
165 .field_name = reg_name ## __ ## field_name ## post_fix
/drivers/gpu/drm/amd/display/dc/gpio/dcn20/
Dhw_factory_dcn20.c62 #define SF_HPD(reg_name, field_name, post_fix)\ argument
63 .field_name = HPD0_ ## reg_name ## __ ## field_name ## post_fix
69 #define SF(reg_name, field_name, post_fix)\ argument
70 .field_name = reg_name ## __ ## field_name ## post_fix
102 #define SF_DDC(reg_name, field_name, post_fix)\ argument
103 .field_name = reg_name ## __ ## field_name ## post_fix
156 #define SF_GENERIC(reg_name, field_name, post_fix)\ argument
157 .field_name = reg_name ## __ ## field_name ## post_fix
/drivers/gpu/drm/amd/display/dc/gpio/dce120/
Dhw_factory_dce120.c46 #define SF_HPD(reg_name, field_name, post_fix)\ argument
47 .field_name = HPD0_ ## reg_name ## __ ## field_name ## post_fix
50 #define SF_HPD(reg_name, field_name, post_fix)\ argument
51 .field_name = HPD0_ ## reg_name ## __ ## field_name ## post_fix
96 #define SF_DDC(reg_name, field_name, post_fix)\ argument
97 .field_name = reg_name ## __ ## field_name ## post_fix
/drivers/gpu/drm/amd/display/dc/gpio/dcn10/
Dhw_factory_dcn10.c47 #define SF_HPD(reg_name, field_name, post_fix)\ argument
48 .field_name = HPD0_ ## reg_name ## __ ## field_name ## post_fix
92 #define SF_DDC(reg_name, field_name, post_fix)\ argument
93 .field_name = reg_name ## __ ## field_name ## post_fix
128 #define SF_GENERIC(reg_name, field_name, post_fix)\ argument
129 .field_name = reg_name ## __ ## field_name ## post_fix
/drivers/gpu/drm/amd/display/dc/gpio/dce110/
Dhw_factory_dce110.c42 #define SF_HPD(reg_name, field_name, post_fix)\ argument
43 .field_name = reg_name ## __ ## field_name ## post_fix
83 #define SF_DDC(reg_name, field_name, post_fix)\ argument
84 .field_name = reg_name ## __ ## field_name ## post_fix
/drivers/gpu/drm/amd/display/dc/dcn20/
Ddcn20_dccg.h44 #define DCCG_SF(reg_name, field_name, post_fix)\ argument
45 .field_name = reg_name ## __ ## field_name ## post_fix
47 #define DCCG_SFI(reg_name, field_name, field_prefix, inst, post_fix)\ argument
48 ….field_prefix ## _ ## field_name[inst] = reg_name ## __ ## field_prefix ## inst ## _ ## field_name…
Ddcn20_vmid.c38 #define FN(reg_name, field_name) \ argument
39 vmid->shifts->field_name, vmid->masks->field_name
Ddcn20_dccg.c39 #define FN(reg_name, field_name) \ argument
40 dccg_dcn->dccg_shift->field_name, dccg_dcn->dccg_mask->field_name
Ddcn20_hubbub.c38 #define FN(reg_name, field_name) \ argument
39 hubbub1->shifts->field_name, hubbub1->masks->field_name
48 #define FN(reg_name, field_name) \ argument
49 hubbub1->shifts->field_name, hubbub1->masks->field_name
/drivers/clk/bcm/
Dclk-kona-setup.c179 static bool bit_posn_valid(u32 bit_posn, const char *field_name, in bit_posn_valid() argument
186 field_name, clock_name, bit_posn, limit); in bit_posn_valid()
199 static bool bitfield_valid(u32 shift, u32 width, const char *field_name, in bitfield_valid() argument
206 field_name, clock_name); in bitfield_valid()
211 field_name, clock_name, shift, width, limit); in bitfield_valid()
253 static bool gate_valid(struct bcm_clk_gate *gate, const char *field_name, in gate_valid() argument
291 static bool sel_valid(struct bcm_clk_sel *sel, const char *field_name, in sel_valid() argument
294 if (!bitfield_valid(sel->shift, sel->width, field_name, clock_name)) in sel_valid()
335 static bool div_valid(struct bcm_clk_div *div, const char *field_name, in div_valid() argument
342 field_name, clock_name); in div_valid()
[all …]
/drivers/gpu/drm/amd/display/dc/bios/
Dbios_parser_helper.c54 #define FN(reg_name, field_name) \ argument
55 ATOM_ ## field_name ## _SHIFT, ATOM_ ## field_name
/drivers/gpu/drm/amd/display/dc/dcn10/
Ddcn10_ipp.c36 #define FN(reg_name, field_name) \ argument
37 ippn10->ipp_shift->field_name, ippn10->ipp_mask->field_name
Ddcn10_dwb.c41 #define FN(reg_name, field_name) \ argument
42 dwbc10->dwbc_shift->field_name, dwbc10->dwbc_mask->field_name
/drivers/gpu/drm/amd/display/dc/dcn30/
Ddcn30_dccg.c37 #define FN(reg_name, field_name) \ argument
38 dccg_dcn->dccg_shift->field_name, dccg_dcn->dccg_mask->field_name
Ddcn30_vpg.c38 #define FN(reg_name, field_name) \ argument
39 vpg3->vpg_shift->field_name, vpg3->vpg_mask->field_name
Ddcn30_afmt.c38 #define FN(reg_name, field_name) \ argument
39 afmt3->afmt_shift->field_name, afmt3->afmt_mask->field_name
/drivers/gpu/drm/amd/display/dc/gpio/
Dhw_generic.c39 #define FN(reg_name, field_name) \ argument
40 generic->shifts->field_name, generic->masks->field_name
Dhw_hpd.c39 #define FN(reg_name, field_name) \ argument
40 hpd->shifts->field_name, hpd->masks->field_name
Dhw_gpio.c34 #define FN(reg_name, field_name) \ argument
35 gpio->regs->field_name ## _shift, gpio->regs->field_name ## _mask
/drivers/gpu/drm/amd/display/dc/clk_mgr/dce60/
Ddce60_clk_mgr.c50 #define FN(reg_name, field_name) \ argument
51 clk_mgr->clk_mgr_shift->field_name, clk_mgr->clk_mgr_mask->field_name
/drivers/gpu/drm/amd/display/dc/gpio/dce80/
Dhw_factory_dce80.c83 #define SF_DDC(reg_name, field_name, post_fix)\ argument
84 .field_name = reg_name ## __ ## field_name ## post_fix
/drivers/gpu/drm/amd/display/dc/gpio/dce60/
Dhw_factory_dce60.c83 #define SF_DDC(reg_name, field_name, post_fix)\ argument
84 .field_name = reg_name ## __ ## field_name ## post_fix
/drivers/gpu/drm/amd/display/dc/dce/
Ddce_panel_cntl.h59 #define DCE_PANEL_CNTL_SF(reg_name, field_name, post_fix)\ argument
60 .field_name = reg_name ## __ ## field_name ## post_fix
/drivers/gpu/drm/amd/display/dc/dce120/
Ddce120_hw_sequencer.c46 #define FN(reg_name, field_name) \ argument
47 hws->shifts->field_name, hws->masks->field_name

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