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Searched refs:field_val (Results 1 – 5 of 5) sorted by relevance

/drivers/gpu/drm/amd/amdgpu/
Dvega10_ih.c683 uint32_t data, def, field_val; in vega10_ih_update_clockgating_state() local
687 field_val = enable ? 0 : 1; in vega10_ih_update_clockgating_state()
694 IH_RETRY_INT_CAM_MEM_CLK_SOFT_OVERRIDE, field_val); in vega10_ih_update_clockgating_state()
696 IH_BUFFER_MEM_CLK_SOFT_OVERRIDE, field_val); in vega10_ih_update_clockgating_state()
700 DBUS_MUX_CLK_SOFT_OVERRIDE, field_val); in vega10_ih_update_clockgating_state()
702 OSSSYS_SHARE_CLK_SOFT_OVERRIDE, field_val); in vega10_ih_update_clockgating_state()
704 LIMIT_SMN_CLK_SOFT_OVERRIDE, field_val); in vega10_ih_update_clockgating_state()
706 DYN_CLK_SOFT_OVERRIDE, field_val); in vega10_ih_update_clockgating_state()
708 REG_CLK_SOFT_OVERRIDE, field_val); in vega10_ih_update_clockgating_state()
Dnavi10_ih.c766 uint32_t data, def, field_val; in navi10_ih_update_clockgating_state() local
770 field_val = enable ? 0 : 1; in navi10_ih_update_clockgating_state()
772 DBUS_MUX_CLK_SOFT_OVERRIDE, field_val); in navi10_ih_update_clockgating_state()
774 OSSSYS_SHARE_CLK_SOFT_OVERRIDE, field_val); in navi10_ih_update_clockgating_state()
776 LIMIT_SMN_CLK_SOFT_OVERRIDE, field_val); in navi10_ih_update_clockgating_state()
778 DYN_CLK_SOFT_OVERRIDE, field_val); in navi10_ih_update_clockgating_state()
780 REG_CLK_SOFT_OVERRIDE, field_val); in navi10_ih_update_clockgating_state()
Damdgpu_psp.h348 uint32_t field_val, uint32_t mask, bool check_changed);
Damdgpu.h1124 #define REG_SET_FIELD(orig_val, reg, field, field_val) \ argument
1126 (REG_FIELD_MASK(reg, field) & ((field_val) << REG_FIELD_SHIFT(reg, field))))
/drivers/gpu/drm/amd/include/
Dcgs_common.h123 #define CGS_REG_SET_FIELD(orig_val, reg, field, field_val) \ argument
125 (CGS_REG_FIELD_MASK(reg, field) & ((field_val) << CGS_REG_FIELD_SHIFT(reg, field))))