| /drivers/tty/vt/ |
| D | conmakehash.c | 83 int fp0, fp1, un0, un1; in main() local
139 fp0 = strtol(p, &p1, 0); in main()
163 if ( fp0 < 0 || fp0 >= fontlen ) in main()
167 tblname, fp0); in main()
170 if ( fp1 && (fp1 < fp0 || fp1 >= fontlen) ) in main()
186 for (i=fp0; i<=fp1; i++) in main()
208 tblname, fp0, fp1); in main()
211 if (un1 - un0 != fp1 - fp0) in main()
215 tblname, un0, un1, fp0, fp1); in main()
218 for(i=fp0; i<=fp1; i++) in main()
[all …]
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| /drivers/gpu/drm/gma500/ |
| D | mdfld_device.c | 189 pipe->fp0 = PSB_RVDC32(map->fp0); in mdfld_save_display_registers()
277 PSB_WVDC32(pipe->fp0, map->fp0); in mdfld_restore_display_registers()
293 PSB_WVDC32(pipe->fp0, map->fp0); in mdfld_restore_display_registers()
440 .fp0 = MRST_FPA0,
463 .fp0 = MDFLD_DPLL_DIV0,
485 .fp0 = MRST_FPA0, /* This is what the old code did ?? */
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| D | oaktrail_device.c | 200 p->fp0 = PSB_RVDC32(MRST_FPA0); in oaktrail_save_display_registers()
315 PSB_WVDC32(p->fp0, MRST_FPA0); in oaktrail_restore_display_registers()
455 .fp0 = MRST_FPA0,
479 .fp0 = FPB0,
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| D | psb_intel_display.c | 213 REG_WRITE(map->fp0, fp); in psb_intel_crtc_mode_set()
248 REG_WRITE(map->fp0, fp); in psb_intel_crtc_mode_set()
313 fp = REG_READ(map->fp0); in psb_intel_crtc_clock_get()
322 fp = p->fp0; in psb_intel_crtc_clock_get()
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| D | psb_device.c | 252 .fp0 = FPA0,
276 .fp0 = FPB0,
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| D | gma_display.c | 593 crtc_state->saveFP0 = REG_READ(map->fp0); in gma_crtc_save()
640 REG_WRITE(map->fp0, crtc_state->saveFP0); in gma_crtc_restore()
641 REG_READ(map->fp0); in gma_crtc_restore()
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| D | cdv_device.c | 517 .fp0 = FPA0,
542 .fp0 = FPB0,
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| D | oaktrail_crtc.c | 554 REG_WRITE_WITH_AUX(map->fp0, fp, i); in oaktrail_crtc_mode_set()
563 REG_WRITE_WITH_AUX(map->fp0, fp, i); in oaktrail_crtc_mode_set()
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| D | psb_drv.h | 267 u32 fp0; member
301 u32 fp0; member
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| D | mdfld_intel_display.c | 894 REG_WRITE(map->fp0, 0); in mdfld_crtc_mode_set()
925 REG_WRITE(map->fp0, fp); in mdfld_crtc_mode_set()
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| D | cdv_intel_display.c | 854 fp = REG_READ(map->fp0); in cdv_intel_crtc_clock_get()
862 fp = p->fp0; in cdv_intel_crtc_clock_get()
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| /drivers/video/fbdev/intelfb/ |
| D | intelfbhw.c | 1045 u32 *dpll, *fp0, *fp1; in intelfbhw_mode_to_hw() local
1061 fp0 = &hw->fpb0; in intelfbhw_mode_to_hw()
1073 fp0 = &hw->fpa0; in intelfbhw_mode_to_hw()
1143 *fp0 = (n << FP_N_DIVISOR_SHIFT) | in intelfbhw_mode_to_hw()
1146 *fp1 = *fp0; in intelfbhw_mode_to_hw()
1281 const u32 *dpll, *fp0, *fp1, *pipe_conf; in intelfbhw_program_mode() local
1304 fp0 = &hw->fpb0; in intelfbhw_program_mode()
1328 fp0 = &hw->fpa0; in intelfbhw_program_mode()
1403 OUTREG(fp0_reg, *fp0); in intelfbhw_program_mode()
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| /drivers/gpu/drm/i915/display/ |
| D | intel_dpll_mgr.h | 172 u32 fp0; member
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| D | intel_dpll_mgr.c | 419 hw_state->fp0 = intel_de_read(dev_priv, PCH_FP0(id)); in ibx_pch_dpll_get_hw_state()
432 intel_de_write(dev_priv, PCH_FP0(id), pll->state.hw_state.fp0); in ibx_pch_dpll_prepare()
529 hw_state->fp0, in ibx_dump_hw_state()
4563 hw_state->fp0, in intel_dpll_dump_hw_state()
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| D | intel_display_debugfs.c | 939 seq_printf(m, " fp0: 0x%08x\n", pll->state.hw_state.fp0); in i915_shared_dplls_info()
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| D | intel_display.c | 7533 crtc_state->dpll_hw_state.fp0); in i9xx_set_pll_dividers()
8259 crtc_state->dpll_hw_state.fp0 = fp; in i9xx_update_pll_dividers()
9548 pipe_config->dpll_hw_state.fp0 = intel_de_read(dev_priv, in i9xx_get_pipe_config()
10350 crtc_state->dpll_hw_state.fp0 = fp; in ilk_compute_dpll()
12147 fp = pipe_config->dpll_hw_state.fp0; in i9xx_crtc_clock_get()
13991 PIPE_CONF_CHECK_X(dpll_hw_state.fp0); in intel_pipe_config_compare()
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