| /drivers/clk/spear/ |
| D | clk-frac-synth.c | 47 struct clk_frac *frac = to_clk_frac(hw); in frac_calc_rate() local
48 struct frac_rate_tbl *rtbl = frac->rtbl; in frac_calc_rate()
61 struct clk_frac *frac = to_clk_frac(hw); in clk_frac_round_rate() local
65 frac->rtbl_cnt, &unused); in clk_frac_round_rate()
71 struct clk_frac *frac = to_clk_frac(hw); in clk_frac_recalc_rate() local
75 if (frac->lock) in clk_frac_recalc_rate()
76 spin_lock_irqsave(frac->lock, flags); in clk_frac_recalc_rate()
78 val = readl_relaxed(frac->reg); in clk_frac_recalc_rate()
80 if (frac->lock) in clk_frac_recalc_rate()
81 spin_unlock_irqrestore(frac->lock, flags); in clk_frac_recalc_rate()
[all …]
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| /drivers/clk/mxs/ |
| D | clk-frac.c | 36 struct clk_frac *frac = to_clk_frac(hw); in clk_frac_recalc_rate() local
40 div = readl_relaxed(frac->reg) >> frac->shift; in clk_frac_recalc_rate()
41 div &= (1 << frac->width) - 1; in clk_frac_recalc_rate()
44 return tmp_rate >> frac->width; in clk_frac_recalc_rate()
50 struct clk_frac *frac = to_clk_frac(hw); in clk_frac_round_rate() local
59 tmp <<= frac->width; in clk_frac_round_rate()
67 result = tmp_rate >> frac->width; in clk_frac_round_rate()
68 if ((result << frac->width) < tmp_rate) in clk_frac_round_rate()
76 struct clk_frac *frac = to_clk_frac(hw); in clk_frac_set_rate() local
85 tmp <<= frac->width; in clk_frac_set_rate()
[all …]
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| D | clk-ref.c | 52 u8 frac = (readl_relaxed(ref->reg) >> (ref->idx * 8)) & 0x3f; in clk_ref_recalc_rate() local
55 do_div(tmp, frac); in clk_ref_recalc_rate()
65 u8 frac; in clk_ref_round_rate() local
69 frac = tmp; in clk_ref_round_rate()
71 if (frac < 18) in clk_ref_round_rate()
72 frac = 18; in clk_ref_round_rate()
73 else if (frac > 35) in clk_ref_round_rate()
74 frac = 35; in clk_ref_round_rate()
78 do_div(tmp, frac); in clk_ref_round_rate()
90 u8 frac, shift = ref->idx * 8; in clk_ref_set_rate() local
[all …]
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| /drivers/clk/imx/ |
| D | clk-pfd.c | 56 u8 frac = (readl_relaxed(pfd->reg) >> (pfd->idx * 8)) & 0x3f; in clk_pfd_recalc_rate() local
59 do_div(tmp, frac); in clk_pfd_recalc_rate()
68 u8 frac; in clk_pfd_round_rate() local
72 frac = tmp; in clk_pfd_round_rate()
73 if (frac < 12) in clk_pfd_round_rate()
74 frac = 12; in clk_pfd_round_rate()
75 else if (frac > 35) in clk_pfd_round_rate()
76 frac = 35; in clk_pfd_round_rate()
79 do_div(tmp, frac); in clk_pfd_round_rate()
89 u8 frac; in clk_pfd_set_rate() local
[all …]
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| D | clk-pfdv2.c | 84 u8 frac; in clk_pfdv2_recalc_rate() local
86 frac = (readl_relaxed(pfd->reg) >> pfd->frac_off) in clk_pfdv2_recalc_rate()
89 if (!frac) { in clk_pfdv2_recalc_rate()
96 do_div(tmp, frac); in clk_pfdv2_recalc_rate()
112 u8 frac; in clk_pfdv2_determine_rate() local
119 frac = tmp; in clk_pfdv2_determine_rate()
121 if (frac < 12) in clk_pfdv2_determine_rate()
122 frac = 12; in clk_pfdv2_determine_rate()
123 else if (frac > 35) in clk_pfdv2_determine_rate()
124 frac = 35; in clk_pfdv2_determine_rate()
[all …]
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| /drivers/gpu/drm/amd/display/dc/dcn10/ |
| D | dcn10_hw_sequencer_debug.c | 81 static const unsigned int frac = 1000; in dcn10_get_hubbub_state() local
97 (s->data_urgent * frac) / ref_clk_mhz / frac, (s->data_urgent * frac) / ref_clk_mhz % frac, in dcn10_get_hubbub_state()
98 …(s->pte_meta_urgent * frac) / ref_clk_mhz / frac, (s->pte_meta_urgent * frac) / ref_clk_mhz % frac, in dcn10_get_hubbub_state()
99 (s->sr_enter * frac) / ref_clk_mhz / frac, (s->sr_enter * frac) / ref_clk_mhz % frac, in dcn10_get_hubbub_state()
100 (s->sr_exit * frac) / ref_clk_mhz / frac, (s->sr_exit * frac) / ref_clk_mhz % frac, in dcn10_get_hubbub_state()
101 …(s->dram_clk_chanage * frac) / ref_clk_mhz / frac, (s->dram_clk_chanage * frac) / ref_clk_mhz % fr… in dcn10_get_hubbub_state()
119 static const unsigned int frac = 1000; in dcn10_get_hubp_states() local
156 … (s->min_ttu_vblank * frac) / ref_clk_mhz / frac, (s->min_ttu_vblank * frac) / ref_clk_mhz % frac, in dcn10_get_hubp_states()
157 …(s->qos_level_low_wm * frac) / ref_clk_mhz / frac, (s->qos_level_low_wm * frac) / ref_clk_mhz % fr… in dcn10_get_hubp_states()
158 …(s->qos_level_high_wm * frac) / ref_clk_mhz / frac, (s->qos_level_high_wm * frac) / ref_clk_mhz % … in dcn10_get_hubp_states()
[all …]
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| /drivers/clk/at91/ |
| D | clk-sam9x60-pll.c | 41 u32 frac; member
72 struct sam9x60_frac *frac = to_sam9x60_frac(core); in sam9x60_frac_pll_recalc_rate() local
74 return parent_rate * (frac->mul + 1) + in sam9x60_frac_pll_recalc_rate()
75 DIV_ROUND_CLOSEST_ULL((u64)parent_rate * frac->frac, (1 << 22)); in sam9x60_frac_pll_recalc_rate()
81 struct sam9x60_frac *frac = to_sam9x60_frac(core); in sam9x60_frac_pll_prepare() local
95 (cmul == frac->mul && cfrac == frac->frac)) in sam9x60_frac_pll_prepare()
106 (frac->mul << core->layout->mul_shift) | in sam9x60_frac_pll_prepare()
107 (frac->frac << core->layout->frac_shift)); in sam9x60_frac_pll_prepare()
180 struct sam9x60_frac *frac = to_sam9x60_frac(core); in sam9x60_frac_pll_compute_mul_frac() local
209 frac->mul = nmul - 1; in sam9x60_frac_pll_compute_mul_frac()
[all …]
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| D | clk-audio-pll.c | 84 struct clk_audio_frac *frac = to_clk_audio_frac(hw); in clk_audio_pll_frac_enable() local
86 regmap_update_bits(frac->regmap, AT91_PMC_AUDIO_PLL0, in clk_audio_pll_frac_enable()
88 regmap_update_bits(frac->regmap, AT91_PMC_AUDIO_PLL0, in clk_audio_pll_frac_enable()
91 regmap_update_bits(frac->regmap, AT91_PMC_AUDIO_PLL1, in clk_audio_pll_frac_enable()
92 AT91_PMC_AUDIO_PLL_FRACR_MASK, frac->fracr); in clk_audio_pll_frac_enable()
98 regmap_update_bits(frac->regmap, AT91_PMC_AUDIO_PLL0, in clk_audio_pll_frac_enable()
102 AT91_PMC_AUDIO_PLL_ND(frac->nd)); in clk_audio_pll_frac_enable()
134 struct clk_audio_frac *frac = to_clk_audio_frac(hw); in clk_audio_pll_frac_disable() local
136 regmap_update_bits(frac->regmap, AT91_PMC_AUDIO_PLL0, in clk_audio_pll_frac_disable()
139 regmap_update_bits(frac->regmap, AT91_PMC_AUDIO_PLL0, in clk_audio_pll_frac_disable()
[all …]
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| /drivers/clk/meson/ |
| D | clk-pll.c | 49 !MESON_PARM_APPLICABLE(&pll->frac)) in __pll_round_closest_mult()
57 unsigned int frac, in __pll_params_to_rate() argument
62 if (frac && MESON_PARM_APPLICABLE(&pll->frac)) { in __pll_params_to_rate()
63 u64 frac_rate = (u64)parent_rate * frac; in __pll_params_to_rate()
66 (1 << pll->frac.width)); in __pll_params_to_rate()
77 unsigned int m, n, frac; in meson_clk_pll_recalc_rate() local
91 frac = MESON_PARM_APPLICABLE(&pll->frac) ? in meson_clk_pll_recalc_rate()
92 meson_parm_read(clk->map, &pll->frac) : in meson_clk_pll_recalc_rate()
95 return __pll_params_to_rate(parent_rate, m, n, frac, pll); in meson_clk_pll_recalc_rate()
104 unsigned int frac_max = (1 << pll->frac.width); in __pll_params_with_frac()
[all …]
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| D | clk-mpll.c | 50 uint64_t frac = do_div(div, requested_rate); in params_from_rate() local
52 frac *= SDM_DEN; in params_from_rate()
55 *sdm = DIV_ROUND_CLOSEST_ULL(frac, requested_rate); in params_from_rate()
57 *sdm = DIV_ROUND_UP_ULL(frac, requested_rate); in params_from_rate()
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| /drivers/gpu/drm/meson/ |
| D | meson_vclk.c | 491 unsigned int frac, unsigned int od1, in meson_hdmi_pll_set_params() argument
498 if (frac) in meson_hdmi_pll_set_params()
500 0x00004000 | frac); in meson_hdmi_pll_set_params()
519 regmap_write(priv->hhi, HHI_HDMI_PLL_CNTL2, 0x800cb000 | frac); in meson_hdmi_pll_set_params()
542 regmap_write(priv->hhi, HHI_HDMI_PLL_CNTL2, frac); in meson_hdmi_pll_set_params()
547 if (frac < 0x10000) { in meson_hdmi_pll_set_params()
643 unsigned int frac; in meson_hdmi_pll_get_frac() local
659 frac = div_u64((u64)pll_freq * (u64)frac_max, parent_freq); in meson_hdmi_pll_get_frac()
661 if (frac_m > frac) in meson_hdmi_pll_get_frac()
663 frac -= frac_m; in meson_hdmi_pll_get_frac()
[all …]
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| /drivers/clk/rockchip/ |
| D | clk.c | 142 struct rockchip_clk_frac *frac = to_rockchip_clk_frac_nb(nb); in rockchip_clk_frac_notifier_cb() local
143 struct clk_mux *frac_mux = &frac->mux; in rockchip_clk_frac_notifier_cb()
149 frac->rate_change_idx = in rockchip_clk_frac_notifier_cb()
150 frac->mux_ops->get_parent(&frac_mux->hw); in rockchip_clk_frac_notifier_cb()
151 if (frac->rate_change_idx != frac->mux_frac_idx) { in rockchip_clk_frac_notifier_cb()
152 frac->mux_ops->set_parent(&frac_mux->hw, in rockchip_clk_frac_notifier_cb()
153 frac->mux_frac_idx); in rockchip_clk_frac_notifier_cb()
154 frac->rate_change_remuxed = 1; in rockchip_clk_frac_notifier_cb()
163 if (frac->rate_change_remuxed) { in rockchip_clk_frac_notifier_cb()
164 frac->mux_ops->set_parent(&frac_mux->hw, in rockchip_clk_frac_notifier_cb()
[all …]
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| D | clk-pll.c | 159 rate->frac = ((pllcon >> RK3036_PLLCON2_FRAC_SHIFT) in rockchip_rk3036_pll_get_params()
177 u64 frac_rate64 = prate * cur.frac; in rockchip_rk3036_pll_recalc_rate()
202 rate->postdiv2, rate->dsmpd, rate->frac); in rockchip_rk3036_pll_set_params()
231 pllcon |= rate->frac << RK3036_PLLCON2_FRAC_SHIFT; in rockchip_rk3036_pll_set_params()
319 cur.dsmpd, cur.frac); in rockchip_rk3036_pll_init()
322 rate->dsmpd, rate->frac); in rockchip_rk3036_pll_init()
327 (!cur.dsmpd && (rate->frac != cur.frac))) { in rockchip_rk3036_pll_init()
637 rate->frac = ((pllcon >> RK3399_PLLCON2_FRAC_SHIFT) in rockchip_rk3399_pll_get_params()
659 u64 frac_rate64 = prate * cur.frac; in rockchip_rk3399_pll_recalc_rate()
684 rate->postdiv2, rate->dsmpd, rate->frac); in rockchip_rk3399_pll_set_params()
[all …]
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| /drivers/net/ethernet/marvell/mvpp2/ |
| D | mvpp2_tai.c | 104 static void mvpp2_tai_write_tlv(const struct timespec64 *ts, u32 frac, in mvpp2_tai_write_tlv() argument
112 mvpp2_tai_write(frac >> 16, base + MVPP22_TAI_TLV_FRAC_HIGH); in mvpp2_tai_write_tlv()
113 mvpp2_tai_write(frac, base + MVPP22_TAI_TLV_FRAC_LOW); in mvpp2_tai_write_tlv()
170 s32 frac; in mvpp22_tai_adjfine() local
187 frac = -val; in mvpp22_tai_adjfine()
192 frac = val; in mvpp22_tai_adjfine()
197 mvpp2_tai_write(frac >> 16, base + MVPP22_TAI_TLV_FRAC_HIGH); in mvpp22_tai_adjfine()
198 mvpp2_tai_write(frac, base + MVPP22_TAI_TLV_FRAC_LOW); in mvpp22_tai_adjfine()
314 u32 nano, frac; in mvpp22_tai_set_step() local
317 frac = lower_32_bits(tai->period); in mvpp22_tai_set_step()
[all …]
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| /drivers/clk/qcom/ |
| D | clk-rcg2.c | 417 const struct frac_entry *frac; in clk_edp_pixel_set_rate() local
425 frac = frac_table_810m; in clk_edp_pixel_set_rate()
427 frac = frac_table_675m; in clk_edp_pixel_set_rate()
429 for (; frac->num; frac++) { in clk_edp_pixel_set_rate()
431 request *= frac->den; in clk_edp_pixel_set_rate()
432 request = div_s64(request, frac->num); in clk_edp_pixel_set_rate()
442 f.m = frac->num; in clk_edp_pixel_set_rate()
443 f.n = frac->den; in clk_edp_pixel_set_rate()
463 const struct frac_entry *frac; in clk_edp_pixel_determine_rate() local
475 frac = frac_table_810m; in clk_edp_pixel_determine_rate()
[all …]
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| /drivers/phy/st/ |
| D | phy-stm32-usbphyc.c | 55 u16 frac; member
89 unsigned long long fvco, ndiv, frac; in stm32_usbphyc_get_pll_params() local
107 frac = fvco * (1 << 16); in stm32_usbphyc_get_pll_params()
108 do_div(frac, (clk_rate * 2)); in stm32_usbphyc_get_pll_params()
109 frac = frac - (ndiv * (1 << 16)); in stm32_usbphyc_get_pll_params()
110 pll_params->frac = (u16)frac; in stm32_usbphyc_get_pll_params()
117 u32 ndiv, frac; in stm32_usbphyc_pll_init() local
129 frac = FIELD_PREP(PLLFRACIN, pll_params.frac); in stm32_usbphyc_pll_init()
133 if (pll_params.frac) in stm32_usbphyc_pll_init()
134 usbphyc_pll |= PLLFRACCTL | frac; in stm32_usbphyc_pll_init()
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| /drivers/hwmon/ |
| D | stts751.c | 151 s32 integer1, integer2, frac; in stts751_update_temp() local
171 frac = i2c_smbus_read_byte_data(priv->client, STTS751_REG_TEMP_L); in stts751_update_temp()
172 if (frac < 0) { in stts751_update_temp()
174 "I2C read failed (temp L). ret: %x\n", frac); in stts751_update_temp()
175 return frac; in stts751_update_temp()
186 frac = i2c_smbus_read_byte_data(priv->client, in stts751_update_temp()
188 if (frac < 0) { in stts751_update_temp()
191 frac); in stts751_update_temp()
192 return frac; in stts751_update_temp()
196 priv->temp = stts751_to_deg((integer1 << 8) | frac); in stts751_update_temp()
[all …]
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| /drivers/clk/sunxi-ng/ |
| D | ccu_mult.c | 81 if (ccu_frac_helper_is_enabled(&cm->common, &cm->frac)) in ccu_mult_recalc_rate()
82 return ccu_frac_helper_read_rate(&cm->common, &cm->frac); in ccu_mult_recalc_rate()
111 if (ccu_frac_helper_has_rate(&cm->common, &cm->frac, rate)) { in ccu_mult_set_rate()
112 ccu_frac_helper_enable(&cm->common, &cm->frac); in ccu_mult_set_rate()
114 return ccu_frac_helper_set_rate(&cm->common, &cm->frac, in ccu_mult_set_rate()
117 ccu_frac_helper_disable(&cm->common, &cm->frac); in ccu_mult_set_rate()
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| D | ccu_nm.c | 86 if (ccu_frac_helper_is_enabled(&nm->common, &nm->frac)) { in ccu_nm_recalc_rate()
87 rate = ccu_frac_helper_read_rate(&nm->common, &nm->frac); in ccu_nm_recalc_rate()
143 if (ccu_frac_helper_has_rate(&nm->common, &nm->frac, rate)) { in ccu_nm_round_rate()
181 if (ccu_frac_helper_has_rate(&nm->common, &nm->frac, rate)) { in ccu_nm_set_rate()
191 ccu_frac_helper_enable(&nm->common, &nm->frac); in ccu_nm_set_rate()
193 return ccu_frac_helper_set_rate(&nm->common, &nm->frac, in ccu_nm_set_rate()
196 ccu_frac_helper_disable(&nm->common, &nm->frac); in ccu_nm_set_rate()
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| D | ccu_nm.h | 28 struct ccu_frac_internal frac; member
72 .frac = _SUNXI_CCU_FRAC(_frac_en, _frac_sel, \
97 .frac = _SUNXI_CCU_FRAC(_frac_en, _frac_sel, \
125 .frac = _SUNXI_CCU_FRAC(_frac_en, _frac_sel, \
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| /drivers/clk/x86/ |
| D | clk-cgu-pll.c | 26 unsigned int div, unsigned int frac, unsigned int frac_div) in lgm_pll_calc_rate() argument
32 frate = rate64 * frac; in lgm_pll_calc_rate()
43 unsigned int div, mult, frac; in lgm_pll_recalc_rate() local
47 frac = lgm_get_clk_val(pll->membase, pll->reg, 2, 24); in lgm_pll_recalc_rate()
52 return lgm_pll_calc_rate(prate, mult, div, frac, BIT(24)); in lgm_pll_recalc_rate()
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| /drivers/gpu/drm/msm/dsi/pll/ |
| D | dsi_pll_10nm.c | 163 u32 frac; in dsi_pll_calc_dec_frac() local
175 div_u64_rem(dec_multiple, multiplier, &frac); in dsi_pll_calc_dec_frac()
192 regs->frac_div_start_low = (frac & 0xff); in dsi_pll_calc_dec_frac()
193 regs->frac_div_start_mid = (frac & 0xff00) >> 8; in dsi_pll_calc_dec_frac()
194 regs->frac_div_start_high = (frac & 0x30000) >> 16; in dsi_pll_calc_dec_frac()
207 u64 frac; in dsi_pll_calc_ssc() local
218 frac = regs->frac_div_start_low | in dsi_pll_calc_ssc()
223 ssc_step_size += frac; in dsi_pll_calc_ssc()
239 regs->decimal_div_start, frac, config->frac_bits); in dsi_pll_calc_ssc()
490 u32 frac; in dsi_pll_10nm_vco_recalc_rate() local
[all …]
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| D | dsi_pll_7nm.c | 164 u32 frac; in dsi_pll_calc_dec_frac() local
176 div_u64_rem(dec_multiple, multiplier, &frac); in dsi_pll_calc_dec_frac()
193 regs->frac_div_start_low = (frac & 0xff); in dsi_pll_calc_dec_frac()
194 regs->frac_div_start_mid = (frac & 0xff00) >> 8; in dsi_pll_calc_dec_frac()
195 regs->frac_div_start_high = (frac & 0x30000) >> 16; in dsi_pll_calc_dec_frac()
208 u64 frac; in dsi_pll_calc_ssc() local
219 frac = regs->frac_div_start_low | in dsi_pll_calc_ssc()
224 ssc_step_size += frac; in dsi_pll_calc_ssc()
240 regs->decimal_div_start, frac, config->frac_bits); in dsi_pll_calc_ssc()
516 u32 frac; in dsi_pll_7nm_vco_recalc_rate() local
[all …]
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| /drivers/clk/zynqmp/ |
| D | pll.c | 137 unsigned long rate, frac; in zynqmp_pll_recalc_rate() local
150 frac = (parent_rate * data) / FRAC_DIV; in zynqmp_pll_recalc_rate()
151 rate = rate + frac; in zynqmp_pll_recalc_rate()
174 long rate_div, frac, m, f; in zynqmp_pll_set_rate() local
185 frac = (parent_rate * f) / FRAC_DIV; in zynqmp_pll_set_rate()
196 return rate + frac; in zynqmp_pll_set_rate()
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| /drivers/media/tuners/ |
| D | fc0011.c | 171 u32 fvco, xin, frac, xdiv, xdivr; in fc0011_set_params() local
209 frac = fvco - xdiv * 18000; in fc0011_set_params()
210 frac = (frac << 15) / 18000; in fc0011_set_params()
211 if (frac >= 16384) in fc0011_set_params()
212 frac += 32786; in fc0011_set_params()
213 if (!frac) in fc0011_set_params()
216 xin = clamp_t(u32, frac, 512, 65024); in fc0011_set_params()
|