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Searched refs:gb_addr_config (Results 1 – 25 of 34) sorted by relevance

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/drivers/gpu/drm/amd/amdgpu/
Dvcn_v1_0.c344 adev->gfx.config.gb_addr_config); in vcn_v1_0_mc_resume_spg_mode()
346 adev->gfx.config.gb_addr_config); in vcn_v1_0_mc_resume_spg_mode()
348 adev->gfx.config.gb_addr_config); in vcn_v1_0_mc_resume_spg_mode()
350 adev->gfx.config.gb_addr_config); in vcn_v1_0_mc_resume_spg_mode()
352 adev->gfx.config.gb_addr_config); in vcn_v1_0_mc_resume_spg_mode()
354 adev->gfx.config.gb_addr_config); in vcn_v1_0_mc_resume_spg_mode()
356 adev->gfx.config.gb_addr_config); in vcn_v1_0_mc_resume_spg_mode()
358 adev->gfx.config.gb_addr_config); in vcn_v1_0_mc_resume_spg_mode()
360 adev->gfx.config.gb_addr_config); in vcn_v1_0_mc_resume_spg_mode()
362 adev->gfx.config.gb_addr_config); in vcn_v1_0_mc_resume_spg_mode()
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Dgfx_v6_0.c1578 u32 gb_addr_config = 0; in gfx_v6_0_constants_init() local
1600 gb_addr_config = TAHITI_GB_ADDR_CONFIG_GOLDEN; in gfx_v6_0_constants_init()
1617 gb_addr_config = TAHITI_GB_ADDR_CONFIG_GOLDEN; in gfx_v6_0_constants_init()
1634 gb_addr_config = VERDE_GB_ADDR_CONFIG_GOLDEN; in gfx_v6_0_constants_init()
1651 gb_addr_config = VERDE_GB_ADDR_CONFIG_GOLDEN; in gfx_v6_0_constants_init()
1668 gb_addr_config = HAINAN_GB_ADDR_CONFIG_GOLDEN; in gfx_v6_0_constants_init()
1694 gb_addr_config &= ~GB_ADDR_CONFIG__ROW_SIZE_MASK; in gfx_v6_0_constants_init()
1698 gb_addr_config |= 0 << GB_ADDR_CONFIG__ROW_SIZE__SHIFT; in gfx_v6_0_constants_init()
1701 gb_addr_config |= 1 << GB_ADDR_CONFIG__ROW_SIZE__SHIFT; in gfx_v6_0_constants_init()
1704 gb_addr_config |= 2 << GB_ADDR_CONFIG__ROW_SIZE__SHIFT; in gfx_v6_0_constants_init()
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Damdgpu_gfx.h130 struct gb_addr_config { struct
165 unsigned gb_addr_config; member
173 struct gb_addr_config gb_addr_config_fields;
Duvd_v4_2.c569 WREG32(mmUVD_UDEC_ADDR_CONFIG, adev->gfx.config.gb_addr_config); in uvd_v4_2_mc_resume()
570 WREG32(mmUVD_UDEC_DB_ADDR_CONFIG, adev->gfx.config.gb_addr_config); in uvd_v4_2_mc_resume()
571 WREG32(mmUVD_UDEC_DBW_ADDR_CONFIG, adev->gfx.config.gb_addr_config); in uvd_v4_2_mc_resume()
Duvd_v3_1.c266 WREG32(mmUVD_UDEC_ADDR_CONFIG, adev->gfx.config.gb_addr_config); in uvd_v3_1_mc_resume()
267 WREG32(mmUVD_UDEC_DB_ADDR_CONFIG, adev->gfx.config.gb_addr_config); in uvd_v3_1_mc_resume()
268 WREG32(mmUVD_UDEC_DBW_ADDR_CONFIG, adev->gfx.config.gb_addr_config); in uvd_v3_1_mc_resume()
Duvd_v5_0.c278 WREG32(mmUVD_UDEC_ADDR_CONFIG, adev->gfx.config.gb_addr_config); in uvd_v5_0_mc_resume()
279 WREG32(mmUVD_UDEC_DB_ADDR_CONFIG, adev->gfx.config.gb_addr_config); in uvd_v5_0_mc_resume()
280 WREG32(mmUVD_UDEC_DBW_ADDR_CONFIG, adev->gfx.config.gb_addr_config); in uvd_v5_0_mc_resume()
Djpeg_v3_0.c339 adev->gfx.config.gb_addr_config); in jpeg_v3_0_start()
341 adev->gfx.config.gb_addr_config); in jpeg_v3_0_start()
Dgfx_v7_0.c1930 WREG32(mmGB_ADDR_CONFIG, adev->gfx.config.gb_addr_config); in gfx_v7_0_constants_init()
1931 WREG32(mmHDP_ADDR_CONFIG, adev->gfx.config.gb_addr_config); in gfx_v7_0_constants_init()
1932 WREG32(mmDMIF_ADDR_CALC, adev->gfx.config.gb_addr_config); in gfx_v7_0_constants_init()
4269 u32 gb_addr_config; in gfx_v7_0_gpu_early_init() local
4290 gb_addr_config = BONAIRE_GB_ADDR_CONFIG_GOLDEN; in gfx_v7_0_gpu_early_init()
4307 gb_addr_config = HAWAII_GB_ADDR_CONFIG_GOLDEN; in gfx_v7_0_gpu_early_init()
4324 gb_addr_config = BONAIRE_GB_ADDR_CONFIG_GOLDEN; in gfx_v7_0_gpu_early_init()
4343 gb_addr_config = BONAIRE_GB_ADDR_CONFIG_GOLDEN; in gfx_v7_0_gpu_early_init()
4395 gb_addr_config &= ~GB_ADDR_CONFIG__ROW_SIZE_MASK; in gfx_v7_0_gpu_early_init()
4399 gb_addr_config |= (0 << GB_ADDR_CONFIG__ROW_SIZE__SHIFT); in gfx_v7_0_gpu_early_init()
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Dgfx_v9_0.c2110 u32 gb_addr_config; in gfx_v9_0_gpu_early_init() local
2122 gb_addr_config = VEGA10_GB_ADDR_CONFIG_GOLDEN; in gfx_v9_0_gpu_early_init()
2130 gb_addr_config = VEGA12_GB_ADDR_CONFIG_GOLDEN; in gfx_v9_0_gpu_early_init()
2139 gb_addr_config = RREG32_SOC15(GC, 0, mmGB_ADDR_CONFIG); in gfx_v9_0_gpu_early_init()
2140 gb_addr_config &= ~0xf3e777ff; in gfx_v9_0_gpu_early_init()
2141 gb_addr_config |= 0x22014042; in gfx_v9_0_gpu_early_init()
2154 gb_addr_config = RAVEN2_GB_ADDR_CONFIG_GOLDEN; in gfx_v9_0_gpu_early_init()
2156 gb_addr_config = RAVEN_GB_ADDR_CONFIG_GOLDEN; in gfx_v9_0_gpu_early_init()
2165 gb_addr_config = RREG32_SOC15(GC, 0, mmGB_ADDR_CONFIG); in gfx_v9_0_gpu_early_init()
2166 gb_addr_config &= ~0xf3e777ff; in gfx_v9_0_gpu_early_init()
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Djpeg_v2_5.c316 adev->gfx.config.gb_addr_config); in jpeg_v2_5_start()
318 adev->gfx.config.gb_addr_config); in jpeg_v2_5_start()
Dgfx_v8_0.c1686 u32 gb_addr_config; in gfx_v8_0_gpu_early_init() local
1708 gb_addr_config = TOPAZ_GB_ADDR_CONFIG_GOLDEN; in gfx_v8_0_gpu_early_init()
1725 gb_addr_config = TONGA_GB_ADDR_CONFIG_GOLDEN; in gfx_v8_0_gpu_early_init()
1740 gb_addr_config = POLARIS11_GB_ADDR_CONFIG_GOLDEN; in gfx_v8_0_gpu_early_init()
1755 gb_addr_config = TONGA_GB_ADDR_CONFIG_GOLDEN; in gfx_v8_0_gpu_early_init()
1772 gb_addr_config = TONGA_GB_ADDR_CONFIG_GOLDEN; in gfx_v8_0_gpu_early_init()
1789 gb_addr_config = CARRIZO_GB_ADDR_CONFIG_GOLDEN; in gfx_v8_0_gpu_early_init()
1806 gb_addr_config = CARRIZO_GB_ADDR_CONFIG_GOLDEN; in gfx_v8_0_gpu_early_init()
1823 gb_addr_config = TONGA_GB_ADDR_CONFIG_GOLDEN; in gfx_v8_0_gpu_early_init()
1878 gb_addr_config = REG_SET_FIELD(gb_addr_config, GB_ADDR_CONFIG, ROW_SIZE, 0); in gfx_v8_0_gpu_early_init()
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Duvd_v6_0.c609 WREG32(mmUVD_UDEC_ADDR_CONFIG, adev->gfx.config.gb_addr_config); in uvd_v6_0_mc_resume()
610 WREG32(mmUVD_UDEC_DB_ADDR_CONFIG, adev->gfx.config.gb_addr_config); in uvd_v6_0_mc_resume()
611 WREG32(mmUVD_UDEC_DBW_ADDR_CONFIG, adev->gfx.config.gb_addr_config); in uvd_v6_0_mc_resume()
Duvd_v7_0.c697 adev->gfx.config.gb_addr_config); in uvd_v7_0_mc_resume()
699 adev->gfx.config.gb_addr_config); in uvd_v7_0_mc_resume()
701 adev->gfx.config.gb_addr_config); in uvd_v7_0_mc_resume()
Dvcn_v2_5.c541 VCN, 0, mmUVD_GFX8_ADDR_CONFIG), adev->gfx.config.gb_addr_config, 0, indirect); in vcn_v2_5_mc_resume_dpg_mode()
1002 adev->gfx.config.gb_addr_config); in vcn_v2_5_start()
1004 adev->gfx.config.gb_addr_config); in vcn_v2_5_start()
Djpeg_v2_0.c348 WREG32_SOC15(JPEG, 0, mmJPEG_DEC_GFX10_ADDR_CONFIG, adev->gfx.config.gb_addr_config); in jpeg_v2_0_start()
Dgfx_v10_0.c4230 u32 gb_addr_config; in gfx_v10_0_gpu_early_init() local
4243 gb_addr_config = RREG32_SOC15(GC, 0, mmGB_ADDR_CONFIG); in gfx_v10_0_gpu_early_init()
4252 gb_addr_config = RREG32_SOC15(GC, 0, mmGB_ADDR_CONFIG); in gfx_v10_0_gpu_early_init()
4254 1 << REG_GET_FIELD(gb_addr_config, GB_ADDR_CONFIG, NUM_PKRS); in gfx_v10_0_gpu_early_init()
4261 adev->gfx.config.gb_addr_config = gb_addr_config; in gfx_v10_0_gpu_early_init()
4264 REG_GET_FIELD(adev->gfx.config.gb_addr_config, in gfx_v10_0_gpu_early_init()
4271 REG_GET_FIELD(adev->gfx.config.gb_addr_config, in gfx_v10_0_gpu_early_init()
4274 REG_GET_FIELD(adev->gfx.config.gb_addr_config, in gfx_v10_0_gpu_early_init()
4277 REG_GET_FIELD(adev->gfx.config.gb_addr_config, in gfx_v10_0_gpu_early_init()
4280 REG_GET_FIELD(adev->gfx.config.gb_addr_config, in gfx_v10_0_gpu_early_init()
Damdgpu_amdkfd_gpuvm.c2261 config->gb_addr_config = adev->gfx.config.gb_addr_config; in amdgpu_amdkfd_get_tile_config()
Dvcn_v2_0.c381 WREG32_SOC15(UVD, 0, mmUVD_GFX10_ADDR_CONFIG, adev->gfx.config.gb_addr_config); in vcn_v2_0_mc_resume()
477 UVD, 0, mmUVD_GFX10_ADDR_CONFIG), adev->gfx.config.gb_addr_config, 0, indirect); in vcn_v2_0_mc_resume_dpg_mode()
Dnv.c243 return adev->gfx.config.gb_addr_config; in nv_get_register_value()
/drivers/gpu/drm/radeon/
Dni.c893 u32 gb_addr_config = 0; in cayman_gpu_init() local
926 gb_addr_config = CAYMAN_GB_ADDR_CONFIG_GOLDEN; in cayman_gpu_init()
1000 gb_addr_config = ARUBA_GB_ADDR_CONFIG_GOLDEN; in cayman_gpu_init()
1031 tmp = (gb_addr_config & NUM_PIPES_MASK) >> NUM_PIPES_SHIFT; in cayman_gpu_init()
1033 tmp = (gb_addr_config & PIPE_INTERLEAVE_SIZE_MASK) >> PIPE_INTERLEAVE_SIZE_SHIFT; in cayman_gpu_init()
1035 tmp = (gb_addr_config & NUM_SHADER_ENGINES_MASK) >> NUM_SHADER_ENGINES_SHIFT; in cayman_gpu_init()
1037 tmp = (gb_addr_config & NUM_GPUS_MASK) >> NUM_GPUS_SHIFT; in cayman_gpu_init()
1039 tmp = (gb_addr_config & MULTI_GPU_TILE_SIZE_MASK) >> MULTI_GPU_TILE_SIZE_SHIFT; in cayman_gpu_init()
1041 tmp = (gb_addr_config & ROW_SIZE_MASK) >> ROW_SIZE_SHIFT; in cayman_gpu_init()
1087 ((gb_addr_config & PIPE_INTERLEAVE_SIZE_MASK) >> PIPE_INTERLEAVE_SIZE_SHIFT) << 8; in cayman_gpu_init()
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Devergreen.c3135 u32 gb_addr_config; in evergreen_gpu_init() local
3176 gb_addr_config = CYPRESS_GB_ADDR_CONFIG_GOLDEN; in evergreen_gpu_init()
3198 gb_addr_config = JUNIPER_GB_ADDR_CONFIG_GOLDEN; in evergreen_gpu_init()
3220 gb_addr_config = REDWOOD_GB_ADDR_CONFIG_GOLDEN; in evergreen_gpu_init()
3243 gb_addr_config = CEDAR_GB_ADDR_CONFIG_GOLDEN; in evergreen_gpu_init()
3265 gb_addr_config = CEDAR_GB_ADDR_CONFIG_GOLDEN; in evergreen_gpu_init()
3293 gb_addr_config = SUMO_GB_ADDR_CONFIG_GOLDEN; in evergreen_gpu_init()
3315 gb_addr_config = SUMO2_GB_ADDR_CONFIG_GOLDEN; in evergreen_gpu_init()
3337 gb_addr_config = BARTS_GB_ADDR_CONFIG_GOLDEN; in evergreen_gpu_init()
3359 gb_addr_config = TURKS_GB_ADDR_CONFIG_GOLDEN; in evergreen_gpu_init()
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Dsi.c3095 u32 gb_addr_config = 0; in si_gpu_init() local
3118 gb_addr_config = TAHITI_GB_ADDR_CONFIG_GOLDEN; in si_gpu_init()
3135 gb_addr_config = TAHITI_GB_ADDR_CONFIG_GOLDEN; in si_gpu_init()
3153 gb_addr_config = VERDE_GB_ADDR_CONFIG_GOLDEN; in si_gpu_init()
3170 gb_addr_config = VERDE_GB_ADDR_CONFIG_GOLDEN; in si_gpu_init()
3187 gb_addr_config = HAINAN_GB_ADDR_CONFIG_GOLDEN; in si_gpu_init()
3223 gb_addr_config &= ~ROW_SIZE_MASK; in si_gpu_init()
3227 gb_addr_config |= ROW_SIZE(0); in si_gpu_init()
3230 gb_addr_config |= ROW_SIZE(1); in si_gpu_init()
3233 gb_addr_config |= ROW_SIZE(2); in si_gpu_init()
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Dcik.c3180 u32 gb_addr_config = RREG32(GB_ADDR_CONFIG); in cik_gpu_init() local
3202 gb_addr_config = BONAIRE_GB_ADDR_CONFIG_GOLDEN; in cik_gpu_init()
3219 gb_addr_config = HAWAII_GB_ADDR_CONFIG_GOLDEN; in cik_gpu_init()
3236 gb_addr_config = BONAIRE_GB_ADDR_CONFIG_GOLDEN; in cik_gpu_init()
3255 gb_addr_config = BONAIRE_GB_ADDR_CONFIG_GOLDEN; in cik_gpu_init()
3289 gb_addr_config &= ~ROW_SIZE_MASK; in cik_gpu_init()
3293 gb_addr_config |= ROW_SIZE(0); in cik_gpu_init()
3296 gb_addr_config |= ROW_SIZE(1); in cik_gpu_init()
3299 gb_addr_config |= ROW_SIZE(2); in cik_gpu_init()
3330 ((gb_addr_config & PIPE_INTERLEAVE_SIZE_MASK) >> PIPE_INTERLEAVE_SIZE_SHIFT) << 8; in cik_gpu_init()
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/drivers/gpu/drm/amd/include/
Dkgd_kfd_interface.h163 uint32_t gb_addr_config; member
/drivers/gpu/drm/amd/amdkfd/
Dkfd_chardev.c1177 args->gb_addr_config = config.gb_addr_config; in kfd_ioctl_get_tile_config()

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