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Searched refs:gen_speed (Results 1 – 8 of 8) sorted by relevance

/drivers/gpu/drm/amd/pm/powerplay/hwmgr/
Dhwmgr_ppt.h96 uint8_t gen_speed; member
Dvega20_hwmgr.c3367 uint32_t gen_speed, lane_width, current_gen_speed, current_lane_width; in vega20_print_clock_levels() local
3460 gen_speed = pptable->PcieGenSpeed[i]; in vega20_print_clock_levels()
3464 (gen_speed == 0) ? "2.5GT/s," : in vega20_print_clock_levels()
3465 (gen_speed == 1) ? "5.0GT/s," : in vega20_print_clock_levels()
3466 (gen_speed == 2) ? "8.0GT/s," : in vega20_print_clock_levels()
3467 (gen_speed == 3) ? "16.0GT/s," : "", in vega20_print_clock_levels()
3475 (current_gen_speed == gen_speed) && in vega20_print_clock_levels()
Dprocess_pptables_v1_0.c536 pcie_record->gen_speed = atom_pcie_record->ucPCIEGenSpeed; in get_pcie_table()
576 pcie_record->gen_speed = atom_pcie_record->ucPCIEGenSpeed; in get_pcie_table()
Dvega10_hwmgr.c1269 bios_pcie_table->entries[i].gen_speed; in vega10_setup_default_pcie_table()
4630 uint32_t gen_speed, lane_width, current_gen_speed, current_lane_width; in vega10_print_clock_levels() local
4693 gen_speed = pptable->PcieGenSpeed[i]; in vega10_print_clock_levels()
4697 (gen_speed == 0) ? "2.5GT/s," : in vega10_print_clock_levels()
4698 (gen_speed == 1) ? "5.0GT/s," : in vega10_print_clock_levels()
4699 (gen_speed == 2) ? "8.0GT/s," : in vega10_print_clock_levels()
4700 (gen_speed == 3) ? "16.0GT/s," : "", in vega10_print_clock_levels()
4707 (current_gen_speed == gen_speed) && in vega10_print_clock_levels()
Dvega10_processpptables.c841 pcie_table->entries[i].gen_speed = in get_pcie_table()
Dsmu7_hwmgr.c613 pcie_table->entries[i].gen_speed), in smu7_setup_default_pcie_table()
/drivers/gpu/drm/amd/pm/swsmu/smu11/
Dnavi10_ppt.c942 uint32_t gen_speed, lane_width; in navi10_print_clk_levels() local
998 gen_speed = smu_v11_0_get_current_pcie_link_speed_level(smu); in navi10_print_clk_levels()
1013 (gen_speed == dpm_context->dpm_tables.pcie_table.pcie_gen[i]) && in navi10_print_clk_levels()
Dsienna_cichlid_ppt.c946 uint32_t gen_speed, lane_width; in sienna_cichlid_print_clk_levels() local
1003 gen_speed = smu_v11_0_get_current_pcie_link_speed_level(smu); in sienna_cichlid_print_clk_levels()
1018 (gen_speed == dpm_context->dpm_tables.pcie_table.pcie_gen[i]) && in sienna_cichlid_print_clk_levels()