| /drivers/gpu/drm/i915/gvt/ |
| D | vgpu.c | 66 gvt_dbg_core("Populate PVINFO PAGE for vGPU %d\n", vgpu->id); in populate_pvinfo_page()
67 gvt_dbg_core("aperture base [GMADR] 0x%llx size 0x%llx\n", in populate_pvinfo_page()
69 gvt_dbg_core("hidden base [GMADR] 0x%llx size=0x%llx\n", in populate_pvinfo_page()
71 gvt_dbg_core("fence size %d\n", vgpu_fence_sz(vgpu)); in populate_pvinfo_page()
159 gvt_dbg_core("type[%d]: %s avail %u low %u high %u fence %u weight %u res %s\n", in intel_gvt_init_vgpu_types()
200 gvt_dbg_core("update type[%d]: %s avail %u low %u high %u fence %u\n", in intel_gvt_update_vgpu_types()
375 gvt_dbg_core("handle %llu low %llu MB high %llu MB fence %llu\n", in __intel_gvt_create_vgpu()
545 gvt_dbg_core("------------------------------------------\n"); in intel_gvt_reset_vgpu_locked()
546 gvt_dbg_core("resseting vgpu%d, dmlr %d, engine_mask %08x\n", in intel_gvt_reset_vgpu_locked()
598 gvt_dbg_core("reset vgpu%d done\n", vgpu->id); in intel_gvt_reset_vgpu_locked()
[all …]
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| D | firmware.c | 193 gvt_dbg_core("Invalid firmware: %s [file] 0x%llx [request] 0x%llx\n", in verify_firmware()
241 gvt_dbg_core("request hw state firmware %s...\n", path); in intel_gvt_load_firmware()
249 gvt_dbg_core("success.\n"); in intel_gvt_load_firmware()
255 gvt_dbg_core("verified.\n"); in intel_gvt_load_firmware()
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| D | gvt.c | 211 gvt_dbg_core("service thread start\n"); in gvt_service_thread()
313 gvt_dbg_core("init gvt device\n"); in intel_gvt_init_device()
378 gvt_dbg_core("gvt device initialization is done\n"); in intel_gvt_init_device()
446 gvt_dbg_core("Running with hypervisor %s in host mode\n", in intel_gvt_register_hypervisor()
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| D | fb_decoder.c | 171 gvt_dbg_core("skl: unsupported bpp:%d\n", bpp); in intel_vgpu_get_stride()
174 gvt_dbg_core("skl: unsupported tile format:%x\n", in intel_vgpu_get_stride()
367 gvt_dbg_core("alpha_plane=0x%x, alpha_force=0x%x\n", in intel_vgpu_decode_cursor_plane()
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| D | opregion.c | 227 gvt_dbg_core("init vgpu%d opregion\n", vgpu->id); in intel_vgpu_init_opregion()
299 gvt_dbg_core("emulate opregion from kernel\n"); in intel_vgpu_opregion_base_write_handler()
334 gvt_dbg_core("vgpu%d: clean vgpu opregion\n", vgpu->id); in intel_vgpu_clean_opregion()
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| D | mmio_context.c | 224 gvt_dbg_core("add lri reg pair 0x%x:0x%x in inhibit ctx, vgpu:%d, rind_id:%d\n", in restore_context_mmio_for_inhibit()
254 gvt_dbg_core("add lri reg pair 0x%x:0x%x in inhibit ctx, vgpu:%d, rind_id:%d\n", in restore_render_mocs_control_for_inhibit()
281 gvt_dbg_core("add lri reg pair 0x%x:0x%x in inhibit ctx, vgpu:%d, rind_id:%d\n", in restore_render_mocs_l3cc_for_inhibit()
390 gvt_dbg_core("invalidate TLB for ring %s\n", engine->name); in handle_tlb_pending_event()
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| D | debug.h | 38 #define gvt_dbg_core(fmt, args...) \ macro
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| D | aperture_gm.c | 93 gvt_dbg_core("vgpu%d: alloc low GM start %llx size %llx\n", vgpu->id, in alloc_vgpu_gm()
96 gvt_dbg_core("vgpu%d: alloc high GM start %llx size %llx\n", vgpu->id, in alloc_vgpu_gm()
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| D | sched_policy.c | 430 gvt_dbg_core("vgpu%d: start schedule\n", vgpu->id); in intel_vgpu_start_schedule()
455 gvt_dbg_core("vgpu%d: stop schedule\n", vgpu->id); in intel_vgpu_stop_schedule()
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| D | scheduler.c | 1114 gvt_dbg_core("workload thread for ring %s started\n", engine->name); in workload_thread()
1201 gvt_dbg_core("clean workload scheduler\n"); in intel_gvt_clean_workload_scheduler()
1218 gvt_dbg_core("init workload scheduler\n"); in intel_gvt_init_workload_scheduler()
1448 gvt_dbg_core("vgpu%d: remove submission ops\n", vgpu->id); in intel_vgpu_select_submission_ops()
1460 gvt_dbg_core("vgpu%d: activate ops [ %s ]\n", in intel_vgpu_select_submission_ops()
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| D | interrupt.c | 431 gvt_dbg_core("vgpu%d: IRQ receive event %d (%s)\n", in handle_default_event_virt()
697 gvt_dbg_core("init irq framework\n"); in intel_gvt_init_irq()
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| D | cfg_space.c | 101 gvt_dbg_core("vgpu-%d power status changed to %d\n", in vgpu_pci_cfg_mem_write()
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| D | kvmgt.c | 723 gvt_dbg_core("intel_vgpu_create succeeded for mdev: %s\n", in intel_vgpu_create()
1352 gvt_dbg_core("vgpu%d ioctl, cmd: %d\n", vgpu->id, cmd); in intel_vgpu_ioctl()
1441 gvt_dbg_core("get region info bar:%d\n", info.index); in intel_vgpu_ioctl()
1450 gvt_dbg_core("get region info index:%d\n", info.index); in intel_vgpu_ioctl()
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| D | dmabuf.c | 244 gvt_dbg_core("invalid drm_format_mod %llx for tiling\n", in vgpu_create_gem()
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| D | handlers.c | 224 gvt_dbg_core("vgpu%d: ips enabled\n", vgpu->id); in gamw_echo_dev_rw_ia_write()
226 gvt_dbg_core("vgpu%d: ips disabled\n", vgpu->id); in gamw_echo_dev_rw_ia_write()
1096 gvt_dbg_core("vgpu%d: %s VGA mode\n", vgpu->id, in vga_control_mmio_write()
1473 gvt_dbg_core("VM(%d) write %x to mailbox, return data0 %x\n", in mailbox_write()
1802 gvt_dbg_core("EXECLIST %s on ring %s\n", in ring_mode_mmio_write()
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| D | gtt.c | 2167 gvt_dbg_core("GMA 0x%lx is not present\n", gma); in intel_vgpu_gma_to_gpa()
2747 gvt_dbg_core("init gtt\n"); in intel_gvt_init_gtt()
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