Searched refs:ih2 (Results 1 – 9 of 9) sorted by relevance
123 struct octeon_instr_ih2 *ih2; in octnet_prepare_pci_cmd_o2() local130 ih2 = (struct octeon_instr_ih2 *)&cmd->cmd2.ih2; in octnet_prepare_pci_cmd_o2()135 ih2->fsz = LIO_PCICMD_O2; in octnet_prepare_pci_cmd_o2()137 ih2->tagtype = ORDERED_TAG; in octnet_prepare_pci_cmd_o2()138 ih2->grp = DEFAULT_POW_GRP; in octnet_prepare_pci_cmd_o2()143 ih2->tag = tag; in octnet_prepare_pci_cmd_o2()145 ih2->tag = LIO_DATA(port); in octnet_prepare_pci_cmd_o2()147 ih2->raw = 1; in octnet_prepare_pci_cmd_o2()148 ih2->qos = (port & 3) + 4; /* map qos based on interface */ in octnet_prepare_pci_cmd_o2()151 ih2->dlengsz = setup->s.u.datasize; in octnet_prepare_pci_cmd_o2()[all …]
589 struct octeon_instr_ih2 *ih2; in octeon_prepare_soft_command() local650 ih2 = (struct octeon_instr_ih2 *)&sc->cmd.cmd2.ih2; in octeon_prepare_soft_command()651 ih2->tagtype = ATOMIC_TAG; in octeon_prepare_soft_command()652 ih2->tag = LIO_CONTROL; in octeon_prepare_soft_command()653 ih2->raw = 1; in octeon_prepare_soft_command()654 ih2->grp = CFG_GET_CTRL_Q_GRP(oct_cfg); in octeon_prepare_soft_command()657 ih2->dlengsz = sc->datasize; in octeon_prepare_soft_command()658 ih2->rs = 1; in octeon_prepare_soft_command()677 ih2->fsz = LIO_SOFTCMDRESP_IH2; in octeon_prepare_soft_command()681 ih2->fsz = LIO_PCICMD_O2; in octeon_prepare_soft_command()[all …]
36 struct octeon_instr_ih2 *ih2; in octeon_alloc_soft_command_resp() local59 ih2 = (struct octeon_instr_ih2 *)&sc->cmd.cmd2.ih2; in octeon_alloc_soft_command_resp()63 ih2->fsz = LIO_SOFTCMDRESP_IH2; in octeon_alloc_soft_command_resp()
212 u64 ih2; member
2286 (&sc->cmd.cmd2.ih2))->dlengsz; in send_nic_timestamp_pkt()
79 if (adev->irq.ih2.ring_size) { in vega10_ih_enable_interrupts()92 adev->irq.ih2.enabled = true; in vega10_ih_enable_interrupts()144 if (adev->irq.ih2.ring_size) { in vega10_ih_disable_interrupts()161 adev->irq.ih2.enabled = false; in vega10_ih_disable_interrupts()162 adev->irq.ih2.rptr = 0; in vega10_ih_disable_interrupts()306 ih = &adev->irq.ih2; in vega10_ih_irq_init()391 else if (ih == &adev->irq.ih2) in vega10_ih_get_wptr()416 else if (ih == &adev->irq.ih2) in vega10_ih_get_wptr()489 else if (ih == &adev->irq.ih2) in vega10_ih_irq_rearm()525 } else if (ih == &adev->irq.ih2) { in vega10_ih_set_rptr()[all …]
124 if (adev->irq.ih2.ring_size) { in navi10_ih_enable_interrupts()137 adev->irq.ih2.enabled = true; in navi10_ih_enable_interrupts()189 if (adev->irq.ih2.ring_size) { in navi10_ih_disable_interrupts()205 adev->irq.ih2.enabled = false; in navi10_ih_disable_interrupts()206 adev->irq.ih2.rptr = 0; in navi10_ih_disable_interrupts()377 ih = &adev->irq.ih2; in navi10_ih_irq_init()463 else if (ih == &adev->irq.ih2) in navi10_ih_get_wptr()487 else if (ih == &adev->irq.ih2) in navi10_ih_get_wptr()559 else if (ih == &adev->irq.ih2) in navi10_ih_irq_rearm()595 } else if (ih == &adev->irq.ih2) { in navi10_ih_set_rptr()[all …]
91 struct amdgpu_ih_ring ih, ih1, ih2; member
206 amdgpu_ih_process(adev, &adev->irq.ih2); in amdgpu_irq_handle_ih2()