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Searched refs:ih_cntl (Results 1 – 8 of 8) sorted by relevance

/drivers/gpu/drm/amd/amdgpu/
Diceland_ih.c62 u32 ih_cntl = RREG32(mmIH_CNTL); in iceland_ih_enable_interrupts() local
65 ih_cntl = REG_SET_FIELD(ih_cntl, IH_CNTL, ENABLE_INTR, 1); in iceland_ih_enable_interrupts()
67 WREG32(mmIH_CNTL, ih_cntl); in iceland_ih_enable_interrupts()
82 u32 ih_cntl = RREG32(mmIH_CNTL); in iceland_ih_disable_interrupts() local
85 ih_cntl = REG_SET_FIELD(ih_cntl, IH_CNTL, ENABLE_INTR, 0); in iceland_ih_disable_interrupts()
87 WREG32(mmIH_CNTL, ih_cntl); in iceland_ih_disable_interrupts()
110 u32 interrupt_cntl, ih_cntl, ih_rb_cntl; in iceland_ih_irq_init() local
148 ih_cntl = RREG32(mmIH_CNTL); in iceland_ih_irq_init()
149 ih_cntl = REG_SET_FIELD(ih_cntl, IH_CNTL, MC_VMID, 0); in iceland_ih_irq_init()
152 ih_cntl = REG_SET_FIELD(ih_cntl, IH_CNTL, RPTR_REARM, 1); in iceland_ih_irq_init()
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Dcz_ih.c62 u32 ih_cntl = RREG32(mmIH_CNTL); in cz_ih_enable_interrupts() local
65 ih_cntl = REG_SET_FIELD(ih_cntl, IH_CNTL, ENABLE_INTR, 1); in cz_ih_enable_interrupts()
67 WREG32(mmIH_CNTL, ih_cntl); in cz_ih_enable_interrupts()
82 u32 ih_cntl = RREG32(mmIH_CNTL); in cz_ih_disable_interrupts() local
85 ih_cntl = REG_SET_FIELD(ih_cntl, IH_CNTL, ENABLE_INTR, 0); in cz_ih_disable_interrupts()
87 WREG32(mmIH_CNTL, ih_cntl); in cz_ih_disable_interrupts()
109 u32 interrupt_cntl, ih_cntl, ih_rb_cntl; in cz_ih_irq_init() local
148 ih_cntl = RREG32(mmIH_CNTL); in cz_ih_irq_init()
149 ih_cntl = REG_SET_FIELD(ih_cntl, IH_CNTL, MC_VMID, 0); in cz_ih_irq_init()
152 ih_cntl = REG_SET_FIELD(ih_cntl, IH_CNTL, RPTR_REARM, 1); in cz_ih_irq_init()
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Dsi_ih.c37 u32 ih_cntl = RREG32(IH_CNTL); in si_ih_enable_interrupts() local
40 ih_cntl |= ENABLE_INTR; in si_ih_enable_interrupts()
42 WREG32(IH_CNTL, ih_cntl); in si_ih_enable_interrupts()
50 u32 ih_cntl = RREG32(IH_CNTL); in si_ih_disable_interrupts() local
53 ih_cntl &= ~ENABLE_INTR; in si_ih_disable_interrupts()
55 WREG32(IH_CNTL, ih_cntl); in si_ih_disable_interrupts()
66 u32 interrupt_cntl, ih_cntl, ih_rb_cntl; in si_ih_irq_init() local
90 ih_cntl = MC_WRREQ_CREDIT(0x10) | MC_WR_CLEAN_CNT(0x10) | MC_VMID(0); in si_ih_irq_init()
92 ih_cntl |= RPTR_REARM; in si_ih_irq_init()
93 WREG32(IH_CNTL, ih_cntl); in si_ih_irq_init()
Dcik_ih.c62 u32 ih_cntl = RREG32(mmIH_CNTL); in cik_ih_enable_interrupts() local
65 ih_cntl |= IH_CNTL__ENABLE_INTR_MASK; in cik_ih_enable_interrupts()
67 WREG32(mmIH_CNTL, ih_cntl); in cik_ih_enable_interrupts()
82 u32 ih_cntl = RREG32(mmIH_CNTL); in cik_ih_disable_interrupts() local
85 ih_cntl &= ~IH_CNTL__ENABLE_INTR_MASK; in cik_ih_disable_interrupts()
87 WREG32(mmIH_CNTL, ih_cntl); in cik_ih_disable_interrupts()
110 u32 interrupt_cntl, ih_cntl, ih_rb_cntl; in cik_ih_irq_init() local
146 ih_cntl = (0x10 << IH_CNTL__MC_WRREQ_CREDIT__SHIFT) | in cik_ih_irq_init()
151 ih_cntl |= IH_CNTL__RPTR_REARM_MASK; in cik_ih_irq_init()
152 WREG32(mmIH_CNTL, ih_cntl); in cik_ih_irq_init()
Dnavi10_ih.c61 u32 ih_cntl, ih_rb_cntl; in force_update_wptr_for_self_int() local
66 ih_cntl = RREG32_SOC15(OSSSYS, 0, mmIH_CNTL2); in force_update_wptr_for_self_int()
69 ih_cntl = REG_SET_FIELD(ih_cntl, IH_CNTL2, in force_update_wptr_for_self_int()
71 ih_cntl = REG_SET_FIELD(ih_cntl, IH_CNTL2, in force_update_wptr_for_self_int()
81 WREG32_SOC15(OSSSYS, 0, mmIH_CNTL2, ih_cntl); in force_update_wptr_for_self_int()
/drivers/gpu/drm/radeon/
Dr600.c3595 u32 ih_cntl = RREG32(IH_CNTL); in r600_enable_interrupts() local
3598 ih_cntl |= ENABLE_INTR; in r600_enable_interrupts()
3600 WREG32(IH_CNTL, ih_cntl); in r600_enable_interrupts()
3608 u32 ih_cntl = RREG32(IH_CNTL); in r600_disable_interrupts() local
3611 ih_cntl &= ~ENABLE_INTR; in r600_disable_interrupts()
3613 WREG32(IH_CNTL, ih_cntl); in r600_disable_interrupts()
3678 u32 interrupt_cntl, ih_cntl, ih_rb_cntl; in r600_irq_init() local
3731 ih_cntl = MC_WRREQ_CREDIT(0x10) | MC_WR_CLEAN_CNT(0x10); in r600_irq_init()
3734 ih_cntl |= RPTR_REARM; in r600_irq_init()
3735 WREG32(IH_CNTL, ih_cntl); in r600_irq_init()
Dsi.c5926 u32 ih_cntl = RREG32(IH_CNTL); in si_enable_interrupts() local
5929 ih_cntl |= ENABLE_INTR; in si_enable_interrupts()
5931 WREG32(IH_CNTL, ih_cntl); in si_enable_interrupts()
5939 u32 ih_cntl = RREG32(IH_CNTL); in si_disable_interrupts() local
5942 ih_cntl &= ~ENABLE_INTR; in si_disable_interrupts()
5944 WREG32(IH_CNTL, ih_cntl); in si_disable_interrupts()
5986 u32 interrupt_cntl, ih_cntl, ih_rb_cntl; in si_irq_init() local
6036 ih_cntl = MC_WRREQ_CREDIT(0x10) | MC_WR_CLEAN_CNT(0x10) | MC_VMID(0); in si_irq_init()
6039 ih_cntl |= RPTR_REARM; in si_irq_init()
6040 WREG32(IH_CNTL, ih_cntl); in si_irq_init()
Dcik.c6825 u32 ih_cntl = RREG32(IH_CNTL); in cik_enable_interrupts() local
6828 ih_cntl |= ENABLE_INTR; in cik_enable_interrupts()
6830 WREG32(IH_CNTL, ih_cntl); in cik_enable_interrupts()
6845 u32 ih_cntl = RREG32(IH_CNTL); in cik_disable_interrupts() local
6848 ih_cntl &= ~ENABLE_INTR; in cik_disable_interrupts()
6850 WREG32(IH_CNTL, ih_cntl); in cik_disable_interrupts()
6950 u32 interrupt_cntl, ih_cntl, ih_rb_cntl; in cik_irq_init() local
7000 ih_cntl = MC_WRREQ_CREDIT(0x10) | MC_WR_CLEAN_CNT(0x10) | MC_VMID(0); in cik_irq_init()
7003 ih_cntl |= RPTR_REARM; in cik_irq_init()
7004 WREG32(IH_CNTL, ih_cntl); in cik_irq_init()