| /drivers/net/ |
| D | sb1000.c | 89 static int card_wait_for_busy_clear(const int ioaddr[],
91 static int card_wait_for_ready(const int ioaddr[], const char* name,
93 static int card_send_command(const int ioaddr[], const char* name,
97 static int sb1000_wait_for_ready(const int ioaddr[], const char* name);
98 static int sb1000_wait_for_ready_clear(const int ioaddr[],
100 static void sb1000_send_command(const int ioaddr[], const char* name,
102 static void sb1000_read_status(const int ioaddr[], unsigned char in[]);
103 static void sb1000_issue_read_command(const int ioaddr[],
107 static int sb1000_reset(const int ioaddr[], const char* name);
108 static int sb1000_check_CRC(const int ioaddr[], const char* name);
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| /drivers/net/ethernet/realtek/ |
| D | atp.c | 193 static int atp_probe1(long ioaddr);
195 static unsigned short eeprom_op(long ioaddr, unsigned int cmd);
198 static void write_packet(long ioaddr, int length, unsigned char *packet, int pad, int mode);
199 static void trigger_send(long ioaddr, int length);
204 static void read_block(long ioaddr, int length, unsigned char *buffer, int data_mode);
232 long ioaddr = *port; in atp_init() local
233 outb(0x57, ioaddr + PAR_DATA); in atp_init()
234 if (inb(ioaddr + PAR_DATA) != 0x57) in atp_init()
236 if (atp_probe1(ioaddr) == 0) in atp_init()
253 static int __init atp_probe1(long ioaddr) in atp_probe1() argument
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| D | atp.h | 108 static inline unsigned char read_byte_mode0(short ioaddr) in read_byte_mode0() argument
112 outb(Ctrl_LNibRead, ioaddr + PAR_CONTROL); in read_byte_mode0()
113 inbyte(ioaddr + PAR_STATUS); in read_byte_mode0()
114 low_nib = (inbyte(ioaddr + PAR_STATUS) >> 3) & 0x0f; in read_byte_mode0()
115 outb(Ctrl_HNibRead, ioaddr + PAR_CONTROL); in read_byte_mode0()
116 inbyte(ioaddr + PAR_STATUS); /* Settling time delay -- needed! */ in read_byte_mode0()
117 inbyte(ioaddr + PAR_STATUS); /* Settling time delay -- needed! */ in read_byte_mode0()
118 return low_nib | ((inbyte(ioaddr + PAR_STATUS) << 1) & 0xf0); in read_byte_mode0()
122 static inline unsigned char read_byte_mode2(short ioaddr) in read_byte_mode2() argument
126 outb(Ctrl_LNibRead, ioaddr + PAR_CONTROL); in read_byte_mode2()
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| /drivers/net/ethernet/samsung/sxgbe/ |
| D | sxgbe_core.c | 21 static void sxgbe_core_init(void __iomem *ioaddr) in sxgbe_core_init() argument
26 regval = readl(ioaddr + SXGBE_CORE_TX_CONFIG_REG); in sxgbe_core_init()
31 writel(regval, ioaddr + SXGBE_CORE_TX_CONFIG_REG); in sxgbe_core_init()
34 regval = readl(ioaddr + SXGBE_CORE_RX_CONFIG_REG); in sxgbe_core_init()
40 writel(regval, ioaddr + SXGBE_CORE_RX_CONFIG_REG); in sxgbe_core_init()
44 static void sxgbe_core_dump_regs(void __iomem *ioaddr) in sxgbe_core_dump_regs() argument
48 static int sxgbe_get_lpi_status(void __iomem *ioaddr, const u32 irq_status) in sxgbe_get_lpi_status() argument
54 lpi_status = readl(ioaddr + SXGBE_CORE_LPI_CTRL_STATUS); in sxgbe_get_lpi_status()
69 static int sxgbe_core_host_irq_status(void __iomem *ioaddr, in sxgbe_core_host_irq_status() argument
74 irq_status = readl(ioaddr + SXGBE_CORE_INT_STATUS_REG); in sxgbe_core_host_irq_status()
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| D | sxgbe_mtl.c | 20 static void sxgbe_mtl_init(void __iomem *ioaddr, unsigned int etsalg, in sxgbe_mtl_init() argument
25 reg_val = readl(ioaddr + SXGBE_MTL_OP_MODE_REG); in sxgbe_mtl_init()
40 writel(reg_val, ioaddr + SXGBE_MTL_OP_MODE_REG); in sxgbe_mtl_init()
50 writel(reg_val, ioaddr + SXGBE_MTL_OP_MODE_REG); in sxgbe_mtl_init()
54 static void sxgbe_mtl_dma_dm_rxqueue(void __iomem *ioaddr) in sxgbe_mtl_dma_dm_rxqueue() argument
56 writel(RX_QUEUE_DYNAMIC, ioaddr + SXGBE_MTL_RXQ_DMAMAP0_REG); in sxgbe_mtl_dma_dm_rxqueue()
57 writel(RX_QUEUE_DYNAMIC, ioaddr + SXGBE_MTL_RXQ_DMAMAP1_REG); in sxgbe_mtl_dma_dm_rxqueue()
58 writel(RX_QUEUE_DYNAMIC, ioaddr + SXGBE_MTL_RXQ_DMAMAP2_REG); in sxgbe_mtl_dma_dm_rxqueue()
61 static void sxgbe_mtl_set_txfifosize(void __iomem *ioaddr, int queue_num, in sxgbe_mtl_set_txfifosize() argument
68 reg_val = readl(ioaddr + SXGBE_MTL_TXQ_OPMODE_REG(queue_num)); in sxgbe_mtl_set_txfifosize()
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| D | sxgbe_dma.c | 21 static int sxgbe_dma_init(void __iomem *ioaddr, int fix_burst, int burst_map) in sxgbe_dma_init() argument
25 reg_val = readl(ioaddr + SXGBE_DMA_SYSBUS_MODE_REG); in sxgbe_dma_init()
38 writel(reg_val, ioaddr + SXGBE_DMA_SYSBUS_MODE_REG); in sxgbe_dma_init()
43 static void sxgbe_dma_channel_init(void __iomem *ioaddr, int cha_num, in sxgbe_dma_channel_init() argument
50 reg_val = readl(ioaddr + SXGBE_DMA_CHA_CTL_REG(cha_num)); in sxgbe_dma_channel_init()
54 writel(reg_val, ioaddr + SXGBE_DMA_CHA_CTL_REG(cha_num)); in sxgbe_dma_channel_init()
56 reg_val = readl(ioaddr + SXGBE_DMA_CHA_TXCTL_REG(cha_num)); in sxgbe_dma_channel_init()
58 writel(reg_val, ioaddr + SXGBE_DMA_CHA_TXCTL_REG(cha_num)); in sxgbe_dma_channel_init()
60 reg_val = readl(ioaddr + SXGBE_DMA_CHA_RXCTL_REG(cha_num)); in sxgbe_dma_channel_init()
62 writel(reg_val, ioaddr + SXGBE_DMA_CHA_RXCTL_REG(cha_num)); in sxgbe_dma_channel_init()
[all …]
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| /drivers/net/ethernet/smsc/ |
| D | smc9194.c | 268 static int smc_probe(struct net_device *dev, int ioaddr);
290 static void smc_reset( int ioaddr );
293 static void smc_enable( int ioaddr );
296 static void smc_shutdown( int ioaddr );
300 static int smc_findirq( int ioaddr );
319 static void smc_reset( int ioaddr ) in smc_reset() argument
324 outw( RCR_SOFTRESET, ioaddr + RCR ); in smc_reset()
331 outw( RCR_CLEAR, ioaddr + RCR ); in smc_reset()
332 outw( TCR_CLEAR, ioaddr + TCR ); in smc_reset()
338 outw( inw( ioaddr + CONTROL ) | CTL_AUTO_RELEASE , ioaddr + CONTROL ); in smc_reset()
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| /drivers/net/ethernet/stmicro/stmmac/ |
| D | dwxgmac2_dma.c | 11 static int dwxgmac2_dma_reset(void __iomem *ioaddr) in dwxgmac2_dma_reset() argument
13 u32 value = readl(ioaddr + XGMAC_DMA_MODE); in dwxgmac2_dma_reset()
16 writel(value | XGMAC_SWR, ioaddr + XGMAC_DMA_MODE); in dwxgmac2_dma_reset()
18 return readl_poll_timeout(ioaddr + XGMAC_DMA_MODE, value, in dwxgmac2_dma_reset()
22 static void dwxgmac2_dma_init(void __iomem *ioaddr, in dwxgmac2_dma_init() argument
25 u32 value = readl(ioaddr + XGMAC_DMA_SYSBUS_MODE); in dwxgmac2_dma_init()
33 writel(value, ioaddr + XGMAC_DMA_SYSBUS_MODE); in dwxgmac2_dma_init()
36 static void dwxgmac2_dma_init_chan(void __iomem *ioaddr, in dwxgmac2_dma_init_chan() argument
39 u32 value = readl(ioaddr + XGMAC_DMA_CH_CONTROL(chan)); in dwxgmac2_dma_init_chan()
44 writel(value, ioaddr + XGMAC_DMA_CH_CONTROL(chan)); in dwxgmac2_dma_init_chan()
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| D | dwmac4_lib.c | 15 int dwmac4_dma_reset(void __iomem *ioaddr) in dwmac4_dma_reset() argument
17 u32 value = readl(ioaddr + DMA_BUS_MODE); in dwmac4_dma_reset()
21 writel(value, ioaddr + DMA_BUS_MODE); in dwmac4_dma_reset()
23 return readl_poll_timeout(ioaddr + DMA_BUS_MODE, value, in dwmac4_dma_reset()
28 void dwmac4_set_rx_tail_ptr(void __iomem *ioaddr, u32 tail_ptr, u32 chan) in dwmac4_set_rx_tail_ptr() argument
30 writel(tail_ptr, ioaddr + DMA_CHAN_RX_END_ADDR(chan)); in dwmac4_set_rx_tail_ptr()
33 void dwmac4_set_tx_tail_ptr(void __iomem *ioaddr, u32 tail_ptr, u32 chan) in dwmac4_set_tx_tail_ptr() argument
35 writel(tail_ptr, ioaddr + DMA_CHAN_TX_END_ADDR(chan)); in dwmac4_set_tx_tail_ptr()
38 void dwmac4_dma_start_tx(void __iomem *ioaddr, u32 chan) in dwmac4_dma_start_tx() argument
40 u32 value = readl(ioaddr + DMA_CHAN_TX_CONTROL(chan)); in dwmac4_dma_start_tx()
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| D | dwxgmac2_core.c | 18 void __iomem *ioaddr = hw->pcsr; in dwxgmac2_core_init() local
21 tx = readl(ioaddr + XGMAC_TX_CONFIG); in dwxgmac2_core_init()
22 rx = readl(ioaddr + XGMAC_RX_CONFIG); in dwxgmac2_core_init()
45 writel(tx, ioaddr + XGMAC_TX_CONFIG); in dwxgmac2_core_init()
46 writel(rx, ioaddr + XGMAC_RX_CONFIG); in dwxgmac2_core_init()
47 writel(XGMAC_INT_DEFAULT_EN, ioaddr + XGMAC_INT_EN); in dwxgmac2_core_init()
50 static void dwxgmac2_set_mac(void __iomem *ioaddr, bool enable) in dwxgmac2_set_mac() argument
52 u32 tx = readl(ioaddr + XGMAC_TX_CONFIG); in dwxgmac2_set_mac()
53 u32 rx = readl(ioaddr + XGMAC_RX_CONFIG); in dwxgmac2_set_mac()
63 writel(tx, ioaddr + XGMAC_TX_CONFIG); in dwxgmac2_set_mac()
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| D | dwmac5.c | 78 void __iomem *ioaddr, bool correctable, in dwmac5_handle_mac_err() argument
83 value = readl(ioaddr + MAC_DPP_FSM_INT_STATUS); in dwmac5_handle_mac_err()
84 writel(value, ioaddr + MAC_DPP_FSM_INT_STATUS); in dwmac5_handle_mac_err()
126 void __iomem *ioaddr, bool correctable, in dwmac5_handle_mtl_err() argument
131 value = readl(ioaddr + MTL_ECC_INT_STATUS); in dwmac5_handle_mtl_err()
132 writel(value, ioaddr + MTL_ECC_INT_STATUS); in dwmac5_handle_mtl_err()
174 void __iomem *ioaddr, bool correctable, in dwmac5_handle_dma_err() argument
179 value = readl(ioaddr + DMA_ECC_INT_STATUS); in dwmac5_handle_dma_err()
180 writel(value, ioaddr + DMA_ECC_INT_STATUS); in dwmac5_handle_dma_err()
186 int dwmac5_safety_feat_config(void __iomem *ioaddr, unsigned int asp) in dwmac5_safety_feat_config() argument
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| D | dwmac4_core.c | 26 void __iomem *ioaddr = hw->pcsr; in dwmac4_core_init() local
27 u32 value = readl(ioaddr + GMAC_CONFIG); in dwmac4_core_init()
48 writel(value, ioaddr + GMAC_CONFIG); in dwmac4_core_init()
56 writel(value, ioaddr + GMAC_INT_EN); in dwmac4_core_init()
62 void __iomem *ioaddr = hw->pcsr; in dwmac4_rx_queue_enable() local
63 u32 value = readl(ioaddr + GMAC_RXQ_CTRL0); in dwmac4_rx_queue_enable()
71 writel(value, ioaddr + GMAC_RXQ_CTRL0); in dwmac4_rx_queue_enable()
77 void __iomem *ioaddr = hw->pcsr; in dwmac4_rx_queue_priority() local
85 value = readl(ioaddr + base_register); in dwmac4_rx_queue_priority()
90 writel(value, ioaddr + base_register); in dwmac4_rx_queue_priority()
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| D | dwmac_lib.c | 16 int dwmac_dma_reset(void __iomem *ioaddr) in dwmac_dma_reset() argument
18 u32 value = readl(ioaddr + DMA_BUS_MODE); in dwmac_dma_reset()
22 writel(value, ioaddr + DMA_BUS_MODE); in dwmac_dma_reset()
24 return readl_poll_timeout(ioaddr + DMA_BUS_MODE, value, in dwmac_dma_reset()
30 void dwmac_enable_dma_transmission(void __iomem *ioaddr) in dwmac_enable_dma_transmission() argument
32 writel(1, ioaddr + DMA_XMT_POLL_DEMAND); in dwmac_enable_dma_transmission()
35 void dwmac_enable_dma_irq(void __iomem *ioaddr, u32 chan, bool rx, bool tx) in dwmac_enable_dma_irq() argument
37 u32 value = readl(ioaddr + DMA_INTR_ENA); in dwmac_enable_dma_irq()
44 writel(value, ioaddr + DMA_INTR_ENA); in dwmac_enable_dma_irq()
47 void dwmac_disable_dma_irq(void __iomem *ioaddr, u32 chan, bool rx, bool tx) in dwmac_disable_dma_irq() argument
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| D | dwmac4_dma.c | 17 static void dwmac4_dma_axi(void __iomem *ioaddr, struct stmmac_axi *axi) in dwmac4_dma_axi() argument
19 u32 value = readl(ioaddr + DMA_SYS_BUS_MODE); in dwmac4_dma_axi()
68 writel(value, ioaddr + DMA_SYS_BUS_MODE); in dwmac4_dma_axi()
71 static void dwmac4_dma_init_rx_chan(void __iomem *ioaddr, in dwmac4_dma_init_rx_chan() argument
78 value = readl(ioaddr + DMA_CHAN_RX_CONTROL(chan)); in dwmac4_dma_init_rx_chan()
80 writel(value, ioaddr + DMA_CHAN_RX_CONTROL(chan)); in dwmac4_dma_init_rx_chan()
84 ioaddr + DMA_CHAN_RX_BASE_ADDR_HI(chan)); in dwmac4_dma_init_rx_chan()
86 writel(lower_32_bits(dma_rx_phy), ioaddr + DMA_CHAN_RX_BASE_ADDR(chan)); in dwmac4_dma_init_rx_chan()
89 static void dwmac4_dma_init_tx_chan(void __iomem *ioaddr, in dwmac4_dma_init_tx_chan() argument
96 value = readl(ioaddr + DMA_CHAN_TX_CONTROL(chan)); in dwmac4_dma_init_tx_chan()
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| /drivers/net/ethernet/3com/ |
| D | 3c509.c | 116 #define EL3WINDOW(win_num) outw(SelectWindow + (win_num), ioaddr + EL3_CMD)
186 static ushort read_eeprom(int ioaddr, int index);
268 static void el3_dev_fill(struct net_device *dev, __be16 *phys_addr, int ioaddr, in el3_dev_fill() argument
274 dev->base_addr = ioaddr; in el3_dev_fill()
283 int ioaddr, isa_irq, if_port, err; in el3_isa_match() local
294 ioaddr = 0x200 + ((iobase & 0x1f) << 4); in el3_isa_match()
307 if (!request_region(ioaddr, EL3_IO_EXTENT, "3c509-isa")) { in el3_isa_match()
316 outb((ioaddr >> 4) | 0xe0, id_port); in el3_isa_match()
319 if (inw(ioaddr) != 0x6d50) { in el3_isa_match()
325 outw(0x0f00, ioaddr + WN0_IRQ); in el3_isa_match()
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| D | 3c574_cs.c | 131 #define EL3WINDOW(win_num) outw(SelectWindow + (win_num), ioaddr + EL3_CMD)
220 static void mdio_sync(unsigned int ioaddr, int bits);
221 static int mdio_read(unsigned int ioaddr, int phy_id, int location);
222 static void mdio_write(unsigned int ioaddr, int phy_id, int location,
224 static unsigned short read_eeprom(unsigned int ioaddr, int index);
308 unsigned int ioaddr; in tc574_config() local
341 ioaddr = dev->base_addr; in tc574_config()
356 phys_addr[i] = htons(read_eeprom(ioaddr, i + 10)); in tc574_config()
370 outw(2<<11, ioaddr + RunnerRdCtrl); in tc574_config()
371 mcr = inb(ioaddr + 2); in tc574_config()
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| D | 3c515.c | 169 #define EL3WINDOW(win_num) outw(SelectWindow + (win_num), ioaddr + EL3_CMD)
361 static int corkscrew_setup(struct net_device *dev, int ioaddr,
432 static int check_device(unsigned ioaddr) in check_device() argument
436 if (!request_region(ioaddr, CORKSCREW_TOTAL_SIZE, "3c515")) in check_device()
439 if ((inw(ioaddr + 0x2002) & 0x1f0) != (ioaddr & 0x1f0)) { in check_device()
440 release_region(ioaddr, CORKSCREW_TOTAL_SIZE); in check_device()
444 outw(EEPROM_Read + 7, ioaddr + Wn0EepromCmd); in check_device()
448 if ((inw(ioaddr + Wn0EepromCmd) & 0x0200) == 0) in check_device()
451 if (inw(ioaddr + Wn0EepromData) != 0x6d50) { in check_device()
452 release_region(ioaddr, CORKSCREW_TOTAL_SIZE); in check_device()
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| D | 3c589_cs.c | 67 #define EL3WINDOW(win_num) outw(SelectWindow + (win_num), ioaddr + EL3_CMD)
163 static u16 read_eeprom(unsigned int ioaddr, int index);
251 unsigned int ioaddr; in tc589_config() local
288 ioaddr = dev->base_addr; in tc589_config()
302 phys_addr[i] = htons(read_eeprom(ioaddr, i)); in tc589_config()
314 outw(0x3f00, ioaddr + 8); in tc589_config()
315 fifo = inl(ioaddr); in tc589_config()
389 static u16 read_eeprom(unsigned int ioaddr, int index) in read_eeprom() argument
392 outw(EEPROM_READ + index, ioaddr + 10); in read_eeprom()
395 if ((inw(ioaddr + 10) & EEPROM_BUSY) == 0) in read_eeprom()
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| /drivers/net/arcnet/ |
| D | com90io.c | 73 int ioaddr = dev->base_addr; in get_buffer_byte() local
75 arcnet_outb(offset >> 8, ioaddr, COM9026_REG_W_ADDR_HI); in get_buffer_byte()
76 arcnet_outb(offset & 0xff, ioaddr, COM9026_REG_W_ADDR_LO); in get_buffer_byte()
78 return arcnet_inb(ioaddr, COM9026_REG_RW_MEMDATA); in get_buffer_byte()
85 int ioaddr = dev->base_addr; in put_buffer_byte() local
87 arcnet_outb(offset >> 8, ioaddr, COM9026_REG_W_ADDR_HI); in put_buffer_byte()
88 arcnet_outb(offset & 0xff, ioaddr, COM9026_REG_W_ADDR_LO); in put_buffer_byte()
90 arcnet_outb(datum, ioaddr, COM9026_REG_RW_MEMDATA); in put_buffer_byte()
98 int ioaddr = dev->base_addr; in get_whole_buffer() local
100 arcnet_outb((offset >> 8) | AUTOINCflag, ioaddr, COM9026_REG_W_ADDR_HI); in get_whole_buffer()
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| D | com20020.c | 65 int ioaddr = dev->base_addr, ofs = 512 * bufnum + offset; in com20020_copy_from_card() local
69 ioaddr, COM20020_REG_W_ADDR_HI); in com20020_copy_from_card()
70 arcnet_outb(ofs & 0xff, ioaddr, COM20020_REG_W_ADDR_LO); in com20020_copy_from_card()
74 arcnet_insb(ioaddr, COM20020_REG_RW_MEMDATA, buf, count)); in com20020_copy_from_card()
80 int ioaddr = dev->base_addr, ofs = 512 * bufnum + offset; in com20020_copy_to_card() local
83 arcnet_outb((ofs >> 8) | AUTOINCflag, ioaddr, COM20020_REG_W_ADDR_HI); in com20020_copy_to_card()
84 arcnet_outb(ofs & 0xff, ioaddr, COM20020_REG_W_ADDR_LO); in com20020_copy_to_card()
88 arcnet_outsb(ioaddr, COM20020_REG_RW_MEMDATA, buf, count)); in com20020_copy_to_card()
94 int ioaddr = dev->base_addr, status; in com20020_check() local
97 arcnet_outb(XTOcfg(3) | RESETcfg, ioaddr, COM20020_REG_W_CONFIG); in com20020_check()
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| /drivers/rtc/ |
| D | rtc-stk17ta8.c | 61 void __iomem *ioaddr; member
75 void __iomem *ioaddr = pdata->ioaddr; in stk17ta8_rtc_set_time() local
78 flags = readb(pdata->ioaddr + RTC_FLAGS); in stk17ta8_rtc_set_time()
79 writeb(flags | RTC_WRITE, pdata->ioaddr + RTC_FLAGS); in stk17ta8_rtc_set_time()
81 writeb(bin2bcd(tm->tm_year % 100), ioaddr + RTC_YEAR); in stk17ta8_rtc_set_time()
82 writeb(bin2bcd(tm->tm_mon + 1), ioaddr + RTC_MONTH); in stk17ta8_rtc_set_time()
83 writeb(bin2bcd(tm->tm_wday) & RTC_DAY_MASK, ioaddr + RTC_DAY); in stk17ta8_rtc_set_time()
84 writeb(bin2bcd(tm->tm_mday), ioaddr + RTC_DATE); in stk17ta8_rtc_set_time()
85 writeb(bin2bcd(tm->tm_hour), ioaddr + RTC_HOURS); in stk17ta8_rtc_set_time()
86 writeb(bin2bcd(tm->tm_min), ioaddr + RTC_MINUTES); in stk17ta8_rtc_set_time()
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| D | rtc-ds1553.c | 60 void __iomem *ioaddr; member
74 void __iomem *ioaddr = pdata->ioaddr; in ds1553_rtc_set_time() local
79 writeb(RTC_WRITE, pdata->ioaddr + RTC_CONTROL); in ds1553_rtc_set_time()
81 writeb(bin2bcd(tm->tm_year % 100), ioaddr + RTC_YEAR); in ds1553_rtc_set_time()
82 writeb(bin2bcd(tm->tm_mon + 1), ioaddr + RTC_MONTH); in ds1553_rtc_set_time()
83 writeb(bin2bcd(tm->tm_wday) & RTC_DAY_MASK, ioaddr + RTC_DAY); in ds1553_rtc_set_time()
84 writeb(bin2bcd(tm->tm_mday), ioaddr + RTC_DATE); in ds1553_rtc_set_time()
85 writeb(bin2bcd(tm->tm_hour), ioaddr + RTC_HOURS); in ds1553_rtc_set_time()
86 writeb(bin2bcd(tm->tm_min), ioaddr + RTC_MINUTES); in ds1553_rtc_set_time()
87 writeb(bin2bcd(tm->tm_sec) & RTC_SECONDS_MASK, ioaddr + RTC_SECONDS); in ds1553_rtc_set_time()
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| D | rtc-ds1742.c | 59 void __iomem *ioaddr = pdata->ioaddr_rtc; in ds1742_rtc_set_time() local
64 writeb(RTC_WRITE, ioaddr + RTC_CONTROL); in ds1742_rtc_set_time()
66 writeb(bin2bcd(tm->tm_year % 100), ioaddr + RTC_YEAR); in ds1742_rtc_set_time()
67 writeb(bin2bcd(tm->tm_mon + 1), ioaddr + RTC_MONTH); in ds1742_rtc_set_time()
68 writeb(bin2bcd(tm->tm_wday) & RTC_DAY_MASK, ioaddr + RTC_DAY); in ds1742_rtc_set_time()
69 writeb(bin2bcd(tm->tm_mday), ioaddr + RTC_DATE); in ds1742_rtc_set_time()
70 writeb(bin2bcd(tm->tm_hour), ioaddr + RTC_HOURS); in ds1742_rtc_set_time()
71 writeb(bin2bcd(tm->tm_min), ioaddr + RTC_MINUTES); in ds1742_rtc_set_time()
72 writeb(bin2bcd(tm->tm_sec) & RTC_SECONDS_MASK, ioaddr + RTC_SECONDS); in ds1742_rtc_set_time()
75 writeb(RTC_WRITE | (century & RTC_CENTURY_MASK), ioaddr + RTC_CENTURY); in ds1742_rtc_set_time()
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| /drivers/net/appletalk/ |
| D | cops.c | 183 static int cops_probe1 (struct net_device *dev, int ioaddr);
184 static int cops_irq (int ioaddr, int board);
277 static int __init cops_probe1(struct net_device *dev, int ioaddr) in cops_probe1() argument
288 if (!request_region(ioaddr, COPS_IO_EXTENT, dev->name)) in cops_probe1()
303 dev->irq = cops_irq(ioaddr, board); in cops_probe1()
330 dev->base_addr = ioaddr; in cops_probe1()
352 dev->name, cardname, ioaddr, dev->irq); in cops_probe1()
356 dev->name, cardname, ioaddr, dev->irq); in cops_probe1()
359 dev->name, cardname, ioaddr); in cops_probe1()
365 release_region(ioaddr, COPS_IO_EXTENT); in cops_probe1()
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| /drivers/net/ethernet/fujitsu/ |
| D | fmvj18x_cs.c | 303 unsigned int ioaddr; in ungermann_try_io_port() local
308 for (ioaddr = 0x300; ioaddr < 0x3e0; ioaddr += 0x20) { in ungermann_try_io_port()
309 link->resource[0]->start = ioaddr; in ungermann_try_io_port()
331 unsigned int ioaddr; in fmvj18x_config() local
440 ioaddr = dev->base_addr; in fmvj18x_config()
444 outb(CONFIG0_RST, ioaddr + CONFIG_0); in fmvj18x_config()
446 outb(CONFIG0_RST_1, ioaddr + CONFIG_0); in fmvj18x_config()
450 outb(BANK_0, ioaddr + CONFIG_1); in fmvj18x_config()
452 outb(BANK_0U, ioaddr + CONFIG_1); in fmvj18x_config()
493 dev->dev_addr[i] = inb(ioaddr + UNGERMANN_MAC_ID + i); in fmvj18x_config()
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