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Searched refs:kiq (Results 1 – 17 of 17) sorted by relevance

/drivers/gpu/drm/amd/amdgpu/
Damdgpu_gfx.c295 struct amdgpu_kiq *kiq = &adev->gfx.kiq; in amdgpu_gfx_kiq_init_ring() local
298 spin_lock_init(&kiq->ring_lock); in amdgpu_gfx_kiq_init_ring()
303 ring->doorbell_index = adev->doorbell_index.kiq; in amdgpu_gfx_kiq_init_ring()
309 ring->eop_gpu_addr = kiq->eop_gpu_addr; in amdgpu_gfx_kiq_init_ring()
328 struct amdgpu_kiq *kiq = &adev->gfx.kiq; in amdgpu_gfx_kiq_fini() local
330 amdgpu_bo_free_kernel(&kiq->eop_obj, &kiq->eop_gpu_addr, NULL); in amdgpu_gfx_kiq_fini()
338 struct amdgpu_kiq *kiq = &adev->gfx.kiq; in amdgpu_gfx_kiq_init() local
341 AMDGPU_GEM_DOMAIN_GTT, &kiq->eop_obj, in amdgpu_gfx_kiq_init()
342 &kiq->eop_gpu_addr, (void **)&hpd); in amdgpu_gfx_kiq_init()
350 r = amdgpu_bo_reserve(kiq->eop_obj, true); in amdgpu_gfx_kiq_init()
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Dgmc_v10_0.c288 if (adev->gfx.kiq.ring.sched.ready && in gmc_v10_0_flush_gpu_tlb()
375 struct amdgpu_ring *ring = &adev->gfx.kiq.ring; in gmc_v10_0_flush_gpu_tlb_pasid()
376 struct amdgpu_kiq *kiq = &adev->gfx.kiq; in gmc_v10_0_flush_gpu_tlb_pasid() local
379 spin_lock(&adev->gfx.kiq.ring_lock); in gmc_v10_0_flush_gpu_tlb_pasid()
381 amdgpu_ring_alloc(ring, kiq->pmf->invalidate_tlbs_size + 8); in gmc_v10_0_flush_gpu_tlb_pasid()
382 kiq->pmf->kiq_invalidate_tlbs(ring, in gmc_v10_0_flush_gpu_tlb_pasid()
387 spin_unlock(&adev->gfx.kiq.ring_lock); in gmc_v10_0_flush_gpu_tlb_pasid()
392 spin_unlock(&adev->gfx.kiq.ring_lock); in gmc_v10_0_flush_gpu_tlb_pasid()
Dgmc_v9_0.c747 if (adev->gfx.kiq.ring.sched.ready && in gmc_v9_0_flush_gpu_tlb()
843 struct amdgpu_ring *ring = &adev->gfx.kiq.ring; in gmc_v9_0_flush_gpu_tlb_pasid()
844 struct amdgpu_kiq *kiq = &adev->gfx.kiq; in gmc_v9_0_flush_gpu_tlb_pasid() local
859 unsigned int ndw = kiq->pmf->invalidate_tlbs_size + 8; in gmc_v9_0_flush_gpu_tlb_pasid()
862 ndw += kiq->pmf->invalidate_tlbs_size; in gmc_v9_0_flush_gpu_tlb_pasid()
864 spin_lock(&adev->gfx.kiq.ring_lock); in gmc_v9_0_flush_gpu_tlb_pasid()
868 kiq->pmf->kiq_invalidate_tlbs(ring, in gmc_v9_0_flush_gpu_tlb_pasid()
870 kiq->pmf->kiq_invalidate_tlbs(ring, in gmc_v9_0_flush_gpu_tlb_pasid()
875 spin_unlock(&adev->gfx.kiq.ring_lock); in gmc_v9_0_flush_gpu_tlb_pasid()
881 spin_unlock(&adev->gfx.kiq.ring_lock); in gmc_v9_0_flush_gpu_tlb_pasid()
Damdgpu_virt.c63 struct amdgpu_kiq *kiq = &adev->gfx.kiq; in amdgpu_virt_kiq_reg_write_reg_wait() local
64 struct amdgpu_ring *ring = &kiq->ring; in amdgpu_virt_kiq_reg_write_reg_wait()
69 spin_lock_irqsave(&kiq->ring_lock, flags); in amdgpu_virt_kiq_reg_write_reg_wait()
78 spin_unlock_irqrestore(&kiq->ring_lock, flags); in amdgpu_virt_kiq_reg_write_reg_wait()
100 spin_unlock_irqrestore(&kiq->ring_lock, flags); in amdgpu_virt_kiq_reg_write_reg_wait()
Dmes_v10_1.c789 struct amdgpu_kiq *kiq = &adev->gfx.kiq;
790 struct amdgpu_ring *kiq_ring = &adev->gfx.kiq.ring;
793 if (!kiq->pmf || !kiq->pmf->kiq_map_queues)
796 r = amdgpu_ring_alloc(kiq_ring, kiq->pmf->map_queues_size);
802 kiq->pmf->kiq_map_queues(kiq_ring, &adev->mes.ring);
Dgfx_v10_0.c3335 adev->gfx.kiq.pmf = &gfx_v10_0_kiq_pm4_funcs; in gfx_v10_0_set_kiq_pm4_funcs()
4355 struct amdgpu_kiq *kiq; in gfx_v10_0_sw_init() local
4391 &adev->gfx.kiq.irq); in gfx_v10_0_sw_init()
4475 kiq = &adev->gfx.kiq; in gfx_v10_0_sw_init()
4476 r = amdgpu_gfx_kiq_init_ring(adev, &kiq->ring, &kiq->irq); in gfx_v10_0_sw_init()
4530 amdgpu_gfx_kiq_free_ring(&adev->gfx.kiq.ring); in gfx_v10_0_sw_fini()
6021 adev->gfx.kiq.ring.sched.ready = false; in gfx_v10_0_cp_compute_enable()
6302 struct amdgpu_kiq *kiq = &adev->gfx.kiq; in gfx_v10_0_kiq_enable_kgq() local
6303 struct amdgpu_ring *kiq_ring = &adev->gfx.kiq.ring; in gfx_v10_0_kiq_enable_kgq()
6306 if (!kiq->pmf || !kiq->pmf->kiq_map_queues) in gfx_v10_0_kiq_enable_kgq()
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Damdgpu_amdkfd_gfx_v10.c310 struct amdgpu_ring *kiq_ring = &adev->gfx.kiq.ring; in kgd_hiq_mqd_load()
325 spin_lock(&adev->gfx.kiq.ring_lock); in kgd_hiq_mqd_load()
352 spin_unlock(&adev->gfx.kiq.ring_lock); in kgd_hiq_mqd_load()
Damdgpu_amdkfd_gfx_v9.c319 struct amdgpu_ring *kiq_ring = &adev->gfx.kiq.ring; in kgd_gfx_v9_hiq_mqd_load()
334 spin_lock(&adev->gfx.kiq.ring_lock); in kgd_gfx_v9_hiq_mqd_load()
361 spin_unlock(&adev->gfx.kiq.ring_lock); in kgd_gfx_v9_hiq_mqd_load()
Damdgpu_doorbell.h42 uint32_t kiq; member
Dvega10_reg_init.c60 adev->doorbell_index.kiq = AMDGPU_DOORBELL64_KIQ; in vega10_doorbell_index_init()
Damdgpu_amdkfd_gfx_v10_3.c295 struct amdgpu_ring *kiq_ring = &adev->gfx.kiq.ring; in hiq_mqd_load_v10_3()
310 spin_lock(&adev->gfx.kiq.ring_lock); in hiq_mqd_load_v10_3()
337 spin_unlock(&adev->gfx.kiq.ring_lock); in hiq_mqd_load_v10_3()
Dgfx_v9_0.c937 adev->gfx.kiq.pmf = &gfx_v9_0_kiq_pm4_funcs; in gfx_v9_0_set_kiq_pm4_funcs()
2260 struct amdgpu_kiq *kiq; in gfx_v9_0_sw_init() local
2374 kiq = &adev->gfx.kiq; in gfx_v9_0_sw_init()
2375 r = amdgpu_gfx_kiq_init_ring(adev, &kiq->ring, &kiq->irq); in gfx_v9_0_sw_init()
2407 amdgpu_gfx_kiq_free_ring(&adev->gfx.kiq.ring); in gfx_v9_0_sw_fini()
3338 adev->gfx.kiq.ring.sched.ready = false; in gfx_v9_0_cp_compute_enable()
3639 (adev->doorbell_index.kiq * 2) << 2); in gfx_v9_0_kiq_init_register()
3796 ring = &adev->gfx.kiq.ring; in gfx_v9_0_kiq_resume()
3974 soc15_grbm_select(adev, adev->gfx.kiq.ring.me, in gfx_v9_0_hw_fini()
3975 adev->gfx.kiq.ring.pipe, in gfx_v9_0_hw_fini()
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Dvega20_reg_init.c60 adev->doorbell_index.kiq = AMDGPU_VEGA20_DOORBELL_KIQ; in vega20_doorbell_index_init()
Damdgpu_gfx.h261 struct amdgpu_kiq kiq; member
Dgfx_v8_0.c1937 struct amdgpu_kiq *kiq; in gfx_v8_0_sw_init() local
2059 kiq = &adev->gfx.kiq; in gfx_v8_0_sw_init()
2060 r = amdgpu_gfx_kiq_init_ring(adev, &kiq->ring, &kiq->irq); in gfx_v8_0_sw_init()
2089 amdgpu_gfx_kiq_free_ring(&adev->gfx.kiq.ring); in gfx_v8_0_sw_fini()
4330 adev->gfx.kiq.ring.sched.ready = false; in gfx_v8_0_cp_compute_enable()
4352 struct amdgpu_ring *kiq_ring = &adev->gfx.kiq.ring; in gfx_v8_0_kiq_kcq_enable()
4703 WREG32(mmCP_MEC_DOORBELL_RANGE_LOWER, adev->doorbell_index.kiq << 2); in gfx_v8_0_set_mec_doorbell_range()
4715 ring = &adev->gfx.kiq.ring; in gfx_v8_0_kiq_resume()
4778 ring = &adev->gfx.kiq.ring; in gfx_v8_0_cp_test_all_rings()
4845 struct amdgpu_ring *kiq_ring = &adev->gfx.kiq.ring; in gfx_v8_0_kcq_disable()
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Dnv.c642 adev->doorbell_index.kiq = AMDGPU_NAVI10_DOORBELL_KIQ; in nv_init_doorbell_index()
Dvi.c1855 adev->doorbell_index.kiq = AMDGPU_DOORBELL_KIQ; in legacy_doorbell_index_init()