| /drivers/gpu/drm/i915/display/ |
| D | intel_combo_phy.c | 305 u8 lane_mask; in intel_combo_phy_power_up_lanes() local
313 lane_mask = PWR_DOWN_LN_3_1_0; in intel_combo_phy_power_up_lanes()
316 lane_mask = PWR_DOWN_LN_3_1; in intel_combo_phy_power_up_lanes()
319 lane_mask = PWR_DOWN_LN_3; in intel_combo_phy_power_up_lanes()
325 lane_mask = PWR_UP_ALL_LANES; in intel_combo_phy_power_up_lanes()
331 lane_mask = lane_reversal ? PWR_DOWN_LN_2_1_0 : in intel_combo_phy_power_up_lanes()
335 lane_mask = lane_reversal ? PWR_DOWN_LN_1_0 : in intel_combo_phy_power_up_lanes()
342 lane_mask = PWR_UP_ALL_LANES; in intel_combo_phy_power_up_lanes()
349 val |= lane_mask << PWR_DOWN_LN_SHIFT; in intel_combo_phy_power_up_lanes()
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| D | intel_tc.c | 86 u32 lane_mask; in intel_tc_port_get_lane_mask() local
88 lane_mask = intel_uncore_read(uncore, in intel_tc_port_get_lane_mask()
91 drm_WARN_ON(&i915->drm, lane_mask == 0xffffffff); in intel_tc_port_get_lane_mask()
94 lane_mask &= DP_LANE_ASSIGNMENT_MASK(dig_port->tc_phy_fia_idx); in intel_tc_port_get_lane_mask()
95 return lane_mask >> DP_LANE_ASSIGNMENT_SHIFT(dig_port->tc_phy_fia_idx); in intel_tc_port_get_lane_mask()
118 u32 lane_mask; in intel_tc_port_fia_max_lane_count() local
125 lane_mask = 0; in intel_tc_port_fia_max_lane_count()
127 lane_mask = intel_tc_port_get_lane_mask(dig_port); in intel_tc_port_fia_max_lane_count()
129 switch (lane_mask) { in intel_tc_port_fia_max_lane_count()
131 MISSING_CASE(lane_mask); in intel_tc_port_fia_max_lane_count()
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| D | intel_dpio_phy.c | 797 unsigned int lane_mask = in chv_phy_pre_pll_enable() local
809 chv_phy_powergate_lanes(encoder, true, lane_mask); in chv_phy_pre_pll_enable()
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| D | intel_dp.c | 3935 unsigned int lane_mask = 0x0; in intel_enable_dp() local
3938 lane_mask = intel_dp_unused_lane_mask(pipe_config->lane_count); in intel_enable_dp()
3941 lane_mask); in intel_enable_dp()
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| /drivers/video/fbdev/omap2/omapfb/dss/ |
| D | core.c | 60 int dss_dsi_enable_pads(int dsi_id, unsigned lane_mask) in dss_dsi_enable_pads() argument
67 return board_data->dsi_enable_pads(dsi_id, lane_mask); in dss_dsi_enable_pads()
70 void dss_dsi_disable_pads(int dsi_id, unsigned lane_mask) in dss_dsi_disable_pads() argument
77 return board_data->dsi_disable_pads(dsi_id, lane_mask); in dss_dsi_disable_pads()
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| D | dss.h | 192 int dss_dsi_enable_pads(int dsi_id, unsigned lane_mask);
193 void dss_dsi_disable_pads(int dsi_id, unsigned lane_mask);
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| /drivers/media/platform/qcom/camss/ |
| D | camss-csiphy.c | 220 u8 lane_mask; in csiphy_get_lane_mask() local
223 lane_mask = 1 << lane_cfg->clk.pos; in csiphy_get_lane_mask()
226 lane_mask |= 1 << lane_cfg->data[i].pos; in csiphy_get_lane_mask()
228 return lane_mask; in csiphy_get_lane_mask()
244 u8 lane_mask = csiphy_get_lane_mask(&cfg->csi2->lane_cfg); in csiphy_stream_on() local
263 if (cfg->combo_mode && (lane_mask & 0x18) == 0x18) { in csiphy_stream_on()
273 csiphy->ops->lanes_enable(csiphy, cfg, pixel_clock, bpp, lane_mask); in csiphy_stream_on()
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| D | camss-csiphy-2ph-1-0.c | 86 u32 pixel_clock, u8 bpp, u8 lane_mask) in csiphy_lanes_enable() argument
102 val |= lane_mask << 1; in csiphy_lanes_enable()
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| D | camss-csiphy.h | 53 u32 pixel_clock, u8 bpp, u8 lane_mask);
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| D | camss-csiphy-3ph-1-0.c | 138 u32 pixel_clock, u8 bpp, u8 lane_mask) in csiphy_lanes_enable() argument
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| /drivers/media/platform/ti-vpe/ |
| D | cal-camerarx.c | 69 u32 lane_mask = CAL_CSI2_COMPLEXIO_CFG_CLOCK_POSITION_MASK; in cal_camerarx_lane_config() local
75 cal_set_field(&val, mipi_csi2->clock_lane + 1, lane_mask); in cal_camerarx_lane_config()
82 lane_mask <<= 4; in cal_camerarx_lane_config()
84 cal_set_field(&val, mipi_csi2->data_lanes[lane] + 1, lane_mask); in cal_camerarx_lane_config()
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| /drivers/media/platform/rcar-vin/ |
| D | rcar-csi2.c | 422 const u32 lane_mask = (1 << lanes) - 1; in rcsi2_wait_phy_start() local
425 (rcsi2_read(priv, PHDLM_REG) & lane_mask) == lane_mask) in rcsi2_wait_phy_start()
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| /drivers/phy/qualcomm/ |
| D | phy-qcom-qmp.c | 90 u8 lane_mask; member
97 .lane_mask = 0xff, \
105 .lane_mask = 0xff, \
112 .lane_mask = l, \
2594 u8 lane_mask) in qcom_qmp_phy_configure_lane() argument
2603 if (!(t->lane_mask & lane_mask)) in qcom_qmp_phy_configure_lane()
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| /drivers/phy/cadence/ |
| D | phy-cadence-torrent.c | 772 u8 lane_mask = (1 << dp->lanes) - 1; in cdns_torrent_dp_set_lanes() local
778 value |= ((~lane_mask) << PMA_TX_ELEC_IDLE_SHIFT) & in cdns_torrent_dp_set_lanes()
790 value = (value & 0x0000FFF0) | (0x0000000E & lane_mask); in cdns_torrent_dp_set_lanes()
796 value = (value & 0x0000FFF0) | (0x0000000F & lane_mask); in cdns_torrent_dp_set_lanes()
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| /drivers/pci/controller/ |
| D | pci-tegra.c | 1977 static int tegra_pcie_get_regulators(struct tegra_pcie *pcie, u32 lane_mask) in tegra_pcie_get_regulators() argument
2025 if (lane_mask & 0x0f) in tegra_pcie_get_regulators()
2029 if (lane_mask & 0x30) in tegra_pcie_get_regulators()
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| /drivers/gpu/drm/omapdrm/dss/ |
| D | dsi.c | 1997 static int dsi_enable_pads(struct dsi_data *dsi, unsigned int lane_mask) in dsi_enable_pads() argument
2000 return dsi_omap4_mux_pads(dsi, lane_mask); in dsi_enable_pads()
2002 return dsi_omap5_mux_pads(dsi, lane_mask); in dsi_enable_pads()
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