| /drivers/scsi/ |
| D | scsi_debug.c | 2996 u32 lb_size = sdebug_sector_size; in comp_write_worker() local
3003 res = !memcmp(fsp + (block * lb_size), arr, (num - rest) * lb_size); in comp_write_worker()
3007 res = memcmp(fsp, arr + ((num - rest) * lb_size), in comp_write_worker()
3008 rest * lb_size); in comp_write_worker()
3013 arr += num * lb_size; in comp_write_worker()
3014 memcpy(fsp + (block * lb_size), arr, (num - rest) * lb_size); in comp_write_worker()
3016 memcpy(fsp, arr + ((num - rest) * lb_size), rest * lb_size); in comp_write_worker()
3571 u32 lb_size = sdebug_sector_size; in resp_write_scat() local
3613 lbdof_blen = lbdof * lb_size; in resp_write_scat()
3651 num_by = num * lb_size; in resp_write_scat()
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| /drivers/gpu/drm/amd/amdgpu/ |
| D | dce_v6_0.c | 505 u32 lb_size; /* line buffer allocated to pipe */ member
789 u32 lb_partitions = wm->lb_size / wm->src_width; in dce_v6_0_check_latency_hiding()
826 u32 lb_size, u32 num_heads) in dce_v6_0_program_watermarks() argument
874 wm_high.lb_size = lb_size; in dce_v6_0_program_watermarks()
901 wm_low.lb_size = lb_size; in dce_v6_0_program_watermarks()
953 lb_vblank_lead_lines = DIV_ROUND_UP(lb_size, mode->crtc_hdisplay); in dce_v6_0_program_watermarks()
1062 u32 num_heads = 0, lb_size; in dce_v6_0_bandwidth_update() local
1077 lb_size = dce_v6_0_line_buffer_adjust(adev, adev->mode_info.crtcs[i], mode0, mode1); in dce_v6_0_bandwidth_update()
1078 dce_v6_0_program_watermarks(adev, adev->mode_info.crtcs[i], lb_size, num_heads); in dce_v6_0_bandwidth_update()
1079 lb_size = dce_v6_0_line_buffer_adjust(adev, adev->mode_info.crtcs[i+1], mode1, mode0); in dce_v6_0_bandwidth_update()
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| D | dce_v8_0.c | 642 u32 lb_size; /* line buffer allocated to pipe */ member
926 u32 lb_partitions = wm->lb_size / wm->src_width; in dce_v8_0_check_latency_hiding()
963 u32 lb_size, u32 num_heads) in dce_v8_0_program_watermarks() argument
1002 wm_high.lb_size = lb_size; in dce_v8_0_program_watermarks()
1041 wm_low.lb_size = lb_size; in dce_v8_0_program_watermarks()
1056 lb_vblank_lead_lines = DIV_ROUND_UP(lb_size, mode->crtc_hdisplay); in dce_v8_0_program_watermarks()
1098 u32 num_heads = 0, lb_size; in dce_v8_0_bandwidth_update() local
1109 lb_size = dce_v8_0_line_buffer_adjust(adev, adev->mode_info.crtcs[i], mode); in dce_v8_0_bandwidth_update()
1111 lb_size, num_heads); in dce_v8_0_bandwidth_update()
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| D | dce_v10_0.c | 707 u32 lb_size; /* line buffer allocated to pipe */ member
991 u32 lb_partitions = wm->lb_size / wm->src_width; in dce_v10_0_check_latency_hiding()
1028 u32 lb_size, u32 num_heads) in dce_v10_0_program_watermarks() argument
1067 wm_high.lb_size = lb_size; in dce_v10_0_program_watermarks()
1106 wm_low.lb_size = lb_size; in dce_v10_0_program_watermarks()
1121 lb_vblank_lead_lines = DIV_ROUND_UP(lb_size, mode->crtc_hdisplay); in dce_v10_0_program_watermarks()
1161 u32 num_heads = 0, lb_size; in dce_v10_0_bandwidth_update() local
1172 lb_size = dce_v10_0_line_buffer_adjust(adev, adev->mode_info.crtcs[i], mode); in dce_v10_0_bandwidth_update()
1174 lb_size, num_heads); in dce_v10_0_bandwidth_update()
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| D | dce_v11_0.c | 733 u32 lb_size; /* line buffer allocated to pipe */ member
1017 u32 lb_partitions = wm->lb_size / wm->src_width; in dce_v11_0_check_latency_hiding()
1054 u32 lb_size, u32 num_heads) in dce_v11_0_program_watermarks() argument
1093 wm_high.lb_size = lb_size; in dce_v11_0_program_watermarks()
1132 wm_low.lb_size = lb_size; in dce_v11_0_program_watermarks()
1147 lb_vblank_lead_lines = DIV_ROUND_UP(lb_size, mode->crtc_hdisplay); in dce_v11_0_program_watermarks()
1187 u32 num_heads = 0, lb_size; in dce_v11_0_bandwidth_update() local
1198 lb_size = dce_v11_0_line_buffer_adjust(adev, adev->mode_info.crtcs[i], mode); in dce_v11_0_bandwidth_update()
1200 lb_size, num_heads); in dce_v11_0_bandwidth_update()
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| /drivers/gpu/drm/radeon/ |
| D | evergreen.c | 1943 u32 lb_size; /* line buffer allocated to pipe */ member
2128 u32 lb_partitions = wm->lb_size / wm->src_width; in evergreen_check_latency_hiding()
2154 u32 lb_size, u32 num_heads) in evergreen_program_watermarks() argument
2202 wm_high.lb_size = lb_size; in evergreen_program_watermarks()
2229 wm_low.lb_size = lb_size; in evergreen_program_watermarks()
2280 radeon_crtc->lb_vblank_lead_lines = DIV_ROUND_UP(lb_size, mode->crtc_hdisplay); in evergreen_program_watermarks()
2325 u32 num_heads = 0, lb_size; in evergreen_bandwidth_update() local
2340 lb_size = evergreen_line_buffer_adjust(rdev, rdev->mode_info.crtcs[i], mode0, mode1); in evergreen_bandwidth_update()
2341 evergreen_program_watermarks(rdev, rdev->mode_info.crtcs[i], lb_size, num_heads); in evergreen_bandwidth_update()
2342 lb_size = evergreen_line_buffer_adjust(rdev, rdev->mode_info.crtcs[i+1], mode1, mode0); in evergreen_bandwidth_update()
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| D | rs690.c | 212 u32 lb_size = 8192; in rs690_line_buffer_adjust() local
253 rdev->mode_info.crtcs[0]->lb_vblank_lead_lines = DIV_ROUND_UP(lb_size, mode1->crtc_hdisplay); in rs690_line_buffer_adjust()
256 rdev->mode_info.crtcs[1]->lb_vblank_lead_lines = DIV_ROUND_UP(lb_size, mode2->crtc_hdisplay); in rs690_line_buffer_adjust()
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| D | si.c | 2069 u32 lb_size; /* line buffer allocated to pipe */ member
2274 u32 lb_partitions = wm->lb_size / wm->src_width; in dce6_check_latency_hiding()
2300 u32 lb_size, u32 num_heads) in dce6_program_watermarks() argument
2351 wm_high.lb_size = lb_size; in dce6_program_watermarks()
2378 wm_low.lb_size = lb_size; in dce6_program_watermarks()
2431 radeon_crtc->lb_vblank_lead_lines = DIV_ROUND_UP(lb_size, mode->crtc_hdisplay); in dce6_program_watermarks()
2468 u32 num_heads = 0, lb_size; in dce6_bandwidth_update() local
2483 lb_size = dce6_line_buffer_adjust(rdev, rdev->mode_info.crtcs[i], mode0, mode1); in dce6_bandwidth_update()
2484 dce6_program_watermarks(rdev, rdev->mode_info.crtcs[i], lb_size, num_heads); in dce6_bandwidth_update()
2485 lb_size = dce6_line_buffer_adjust(rdev, rdev->mode_info.crtcs[i+1], mode1, mode0); in dce6_bandwidth_update()
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| D | cik.c | 8927 u32 lb_size; /* line buffer allocated to pipe */ member
9211 u32 lb_partitions = wm->lb_size / wm->src_width; in dce8_check_latency_hiding()
9248 u32 lb_size, u32 num_heads) in dce8_program_watermarks() argument
9288 wm_high.lb_size = lb_size; in dce8_program_watermarks()
9328 wm_low.lb_size = lb_size; in dce8_program_watermarks()
9345 radeon_crtc->lb_vblank_lead_lines = DIV_ROUND_UP(lb_size, mode->crtc_hdisplay); in dce8_program_watermarks()
9385 u32 num_heads = 0, lb_size; in dce8_bandwidth_update() local
9399 lb_size = dce8_line_buffer_adjust(rdev, rdev->mode_info.crtcs[i], mode); in dce8_bandwidth_update()
9400 dce8_program_watermarks(rdev, rdev->mode_info.crtcs[i], lb_size, num_heads); in dce8_bandwidth_update()
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| D | r100.c | 3220 u32 lb_size = 8192; in r100_bandwidth_update() local
3645 rdev->mode_info.crtcs[0]->lb_vblank_lead_lines = DIV_ROUND_UP(lb_size, mode1->crtc_hdisplay); in r100_bandwidth_update()
3648 rdev->mode_info.crtcs[1]->lb_vblank_lead_lines = DIV_ROUND_UP(lb_size, mode2->crtc_hdisplay); in r100_bandwidth_update()
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