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Searched refs:mmCM0_CM_MEM_PWR_STATUS (Results 1 – 4 of 4) sorted by relevance

/drivers/gpu/drm/amd/include/asic_reg/dcn/
Ddcn_1_0_offset.h3904 #define mmCM0_CM_MEM_PWR_STATUS … macro
Ddcn_2_1_0_offset.h3708 #define mmCM0_CM_MEM_PWR_STATUS … macro
Ddcn_2_0_0_offset.h4646 #define mmCM0_CM_MEM_PWR_STATUS … macro
Ddcn_3_0_0_offset.h4377 #define mmCM0_CM_MEM_PWR_STATUS … macro