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Searched refs:mmDC_GPU_TIMER_READ (Results 1 – 10 of 10) sorted by relevance

/drivers/gpu/drm/amd/include/asic_reg/dce/
Ddce_6_0_d.h1277 #define mmDC_GPU_TIMER_READ 0x1929 macro
Ddce_8_0_d.h1297 #define mmDC_GPU_TIMER_READ 0x1929 macro
Ddce_10_0_d.h1584 #define mmDC_GPU_TIMER_READ 0x482b macro
Ddce_11_0_d.h1409 #define mmDC_GPU_TIMER_READ 0x482b macro
Ddce_11_2_d.h1489 #define mmDC_GPU_TIMER_READ 0x482b macro
Ddce_12_0_offset.h1882 #define mmDC_GPU_TIMER_READ … macro
/drivers/gpu/drm/amd/include/asic_reg/dcn/
Ddcn_1_0_offset.h1074 #define mmDC_GPU_TIMER_READ … macro
Ddcn_2_1_0_offset.h710 #define mmDC_GPU_TIMER_READ … macro
Ddcn_2_0_0_offset.h748 #define mmDC_GPU_TIMER_READ … macro
Ddcn_3_0_0_offset.h641 #define mmDC_GPU_TIMER_READ … macro