Home
last modified time | relevance | path

Searched refs:mmDP0_DP_SEC_CNTL5 (Results 1 – 4 of 4) sorted by relevance

/drivers/gpu/drm/amd/include/asic_reg/dcn/
Ddcn_1_0_offset.h8477 #define mmDP0_DP_SEC_CNTL5 … macro
Ddcn_2_1_0_offset.h9981 #define mmDP0_DP_SEC_CNTL5 … macro
Ddcn_2_0_0_offset.h11074 #define mmDP0_DP_SEC_CNTL5 … macro
Ddcn_3_0_0_offset.h10795 #define mmDP0_DP_SEC_CNTL5 … macro