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Searched refs:mmDP1_DP_SEC_CNTL5_BASE_IDX (Results 1 – 4 of 4) sorted by relevance

/drivers/gpu/drm/amd/include/asic_reg/dcn/
Ddcn_1_0_offset.h8788 #define mmDP1_DP_SEC_CNTL5_BASE_IDX … macro
Ddcn_2_1_0_offset.h10312 #define mmDP1_DP_SEC_CNTL5_BASE_IDX … macro
Ddcn_2_0_0_offset.h11403 #define mmDP1_DP_SEC_CNTL5_BASE_IDX … macro
Ddcn_3_0_0_offset.h11139 #define mmDP1_DP_SEC_CNTL5_BASE_IDX … macro