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Searched refs:mmDP3_DP_SEC_CNTL1_BASE_IDX (Results 1 – 5 of 5) sorted by relevance

/drivers/gpu/drm/amd/include/asic_reg/dcn/
Ddcn_1_0_offset.h9340 #define mmDP3_DP_SEC_CNTL1_BASE_IDX … macro
Ddcn_2_1_0_offset.h10904 #define mmDP3_DP_SEC_CNTL1_BASE_IDX … macro
Ddcn_2_0_0_offset.h11991 #define mmDP3_DP_SEC_CNTL1_BASE_IDX … macro
Ddcn_3_0_0_offset.h11758 #define mmDP3_DP_SEC_CNTL1_BASE_IDX … macro
/drivers/gpu/drm/amd/include/asic_reg/dce/
Ddce_12_0_offset.h11113 #define mmDP3_DP_SEC_CNTL1_BASE_IDX … macro