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Searched refs:mmDPPCLK_CGTT_BLK_CTRL_REG (Results 1 – 4 of 4) sorted by relevance

/drivers/gpu/drm/amd/include/asic_reg/dcn/
Ddcn_1_0_offset.h620 #define mmDPPCLK_CGTT_BLK_CTRL_REG … macro
Ddcn_2_1_0_offset.h254 #define mmDPPCLK_CGTT_BLK_CTRL_REG … macro
Ddcn_2_0_0_offset.h258 #define mmDPPCLK_CGTT_BLK_CTRL_REG … macro
Ddcn_3_0_0_offset.h239 #define mmDPPCLK_CGTT_BLK_CTRL_REG … macro