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Searched refs:mmDP_DTO4_PHASE_BASE_IDX (Results 1 – 4 of 4) sorted by relevance

/drivers/gpu/drm/amd/include/asic_reg/dcn/
Ddcn_1_0_offset.h607 #define mmDP_DTO4_PHASE_BASE_IDX … macro
Ddcn_2_0_0_offset.h245 #define mmDP_DTO4_PHASE_BASE_IDX … macro
Ddcn_3_0_0_offset.h226 #define mmDP_DTO4_PHASE_BASE_IDX … macro
/drivers/gpu/drm/amd/include/asic_reg/dce/
Ddce_12_0_offset.h807 #define mmDP_DTO4_PHASE_BASE_IDX … macro