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Searched refs:mmDSCC1_DSCC_CONFIG0 (Results 1 – 3 of 3) sorted by relevance

/drivers/gpu/drm/amd/include/asic_reg/dcn/
Ddcn_2_1_0_offset.h11638 #define mmDSCC1_DSCC_CONFIG0 … macro
Ddcn_2_0_0_offset.h13768 #define mmDSCC1_DSCC_CONFIG0 … macro
Ddcn_3_0_0_offset.h12871 #define mmDSCC1_DSCC_CONFIG0 … macro