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Searched refs:mmGENFC_WT_1 (Results 1 – 5 of 5) sorted by relevance

/drivers/gpu/drm/amd/include/asic_reg/dcn/
Ddcn_1_0_offset.h128 #define mmGENFC_WT_1 … macro
Ddcn_2_1_0_offset.h80 #define mmGENFC_WT_1 … macro
Ddcn_2_0_0_offset.h114 #define mmGENFC_WT_1 … macro
Ddcn_3_0_0_offset.h95 #define mmGENFC_WT_1 … macro
/drivers/gpu/drm/amd/include/asic_reg/dce/
Ddce_12_0_offset.h636 #define mmGENFC_WT_1 … macro