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Searched refs:mmHUBPREQ5_DST_Y_DELTA_DRQ_LIMIT_BASE_IDX (Results 1 – 2 of 2) sorted by relevance

/drivers/gpu/drm/amd/include/asic_reg/dcn/
Ddcn_2_0_0_offset.h4113 #define mmHUBPREQ5_DST_Y_DELTA_DRQ_LIMIT_BASE_IDX macro
Ddcn_3_0_0_offset.h3748 #define mmHUBPREQ5_DST_Y_DELTA_DRQ_LIMIT_BASE_IDX macro