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Searched refs:mmMC_SEQ_MISC_TIMING2_LP (Results 1 – 7 of 7) sorted by relevance

/drivers/gpu/drm/amd/include/asic_reg/gmc/
Dgmc_6_0_d.h903 #define mmMC_SEQ_MISC_TIMING2_LP 0x0A9E macro
Dgmc_7_1_d.h815 #define mmMC_SEQ_MISC_TIMING2_LP 0xa9e macro
Dgmc_8_1_d.h919 #define mmMC_SEQ_MISC_TIMING2_LP 0xa9e macro
/drivers/gpu/drm/amd/pm/powerplay/smumgr/
Diceland_smumgr.c2408 *out_reg = mmMC_SEQ_MISC_TIMING2_LP; in iceland_check_s0_mc_reg_index()
2625 …cgs_write_register(hwmgr->device, mmMC_SEQ_MISC_TIMING2_LP, cgs_read_register(hwmgr->device, mmMC_… in iceland_initialize_mc_reg_table()
Dtonga_smumgr.c2871 *out_reg = mmMC_SEQ_MISC_TIMING2_LP; in tonga_check_s0_mc_reg_index()
3099 cgs_write_register(hwmgr->device, mmMC_SEQ_MISC_TIMING2_LP, in tonga_initialize_mc_reg_table()
Dci_smumgr.c2480 *out_reg = mmMC_SEQ_MISC_TIMING2_LP; in ci_check_s0_mc_reg_index()
2697 …cgs_write_register(hwmgr->device, mmMC_SEQ_MISC_TIMING2_LP, cgs_read_register(hwmgr->device, mmMC_… in ci_initialize_mc_reg_table()
Dfiji_smumgr.c2529 cgs_write_register(hwmgr->device, mmMC_SEQ_MISC_TIMING2_LP, in fiji_initialize_mc_reg_table()