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Searched refs:mmMPCC0_MPCC_BG_G_Y (Results 1 – 4 of 4) sorted by relevance

/drivers/gpu/drm/amd/include/asic_reg/dcn/
Ddcn_1_0_offset.h5381 #define mmMPCC0_MPCC_BG_G_Y … macro
Ddcn_2_1_0_offset.h5618 #define mmMPCC0_MPCC_BG_G_Y … macro
Ddcn_2_0_0_offset.h6556 #define mmMPCC0_MPCC_BG_G_Y … macro
Ddcn_3_0_0_offset.h13772 #define mmMPCC0_MPCC_BG_G_Y … macro