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Searched refs:mmMPCC3_MPCC_BG_R_CR (Results 1 – 4 of 4) sorted by relevance

/drivers/gpu/drm/amd/include/asic_reg/dcn/
Ddcn_1_0_offset.h5475 #define mmMPCC3_MPCC_BG_R_CR … macro
Ddcn_2_1_0_offset.h5718 #define mmMPCC3_MPCC_BG_R_CR … macro
Ddcn_2_0_0_offset.h6656 #define mmMPCC3_MPCC_BG_R_CR … macro
Ddcn_3_0_0_offset.h13866 #define mmMPCC3_MPCC_BG_R_CR … macro