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Searched refs:mmMPCC4_MPCC_TOP_SEL (Results 1 – 3 of 3) sorted by relevance

/drivers/gpu/drm/amd/include/asic_reg/dcn/
Ddcn_2_1_0_offset.h5734 #define mmMPCC4_MPCC_TOP_SEL … macro
Ddcn_2_0_0_offset.h6672 #define mmMPCC4_MPCC_TOP_SEL … macro
Ddcn_3_0_0_offset.h13880 #define mmMPCC4_MPCC_TOP_SEL … macro