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Searched refs:mmMPCC6_MPCC_BOT_SEL (Results 1 – 2 of 2) sorted by relevance

/drivers/gpu/drm/amd/include/asic_reg/dcn/
Ddcn_2_1_0_offset.h5804 #define mmMPCC6_MPCC_BOT_SEL macro
Ddcn_2_0_0_offset.h6742 #define mmMPCC6_MPCC_BOT_SEL macro