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Searched refs:mmMPLL_CONTROL (Results 1 – 5 of 5) sorted by relevance

/drivers/gpu/drm/amd/pm/powerplay/hwmgr/
Dci_baco.c101 { CMD_WRITE, mmMPLL_CONTROL, 0, 0, 0, 0x00000006 },
Dtonga_baco.c92 { CMD_WRITE, mmMPLL_CONTROL, 0, 0, 0, 0x00000006 },
/drivers/gpu/drm/amd/include/asic_reg/gmc/
Dgmc_6_0_d.h1203 #define mmMPLL_CONTROL 0x0AF5 macro
Dgmc_7_1_d.h868 #define mmMPLL_CONTROL 0xaf5 macro
Dgmc_8_1_d.h972 #define mmMPLL_CONTROL 0xaf5 macro