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Searched refs:mmOTG5_OTG_SPARE_REGISTER (Results 1 – 4 of 4) sorted by relevance

/drivers/gpu/drm/amd/include/asic_reg/dcn/
Ddcn_1_0_offset.h7575 #define mmOTG5_OTG_SPARE_REGISTER … macro
Ddcn_2_1_0_offset.h9213 #define mmOTG5_OTG_SPARE_REGISTER … macro
Ddcn_2_0_0_offset.h10244 #define mmOTG5_OTG_SPARE_REGISTER … macro
Ddcn_3_0_0_offset.h9972 #define mmOTG5_OTG_SPARE_REGISTER … macro