Home
last modified time | relevance | path

Searched refs:mmVM_L2_CNTL4 (Results 1 – 11 of 11) sorted by relevance

/drivers/gpu/drm/amd/amdgpu/
Dgfxhub_v1_0.c176 WREG32_SOC15_RLC(GC, 0, mmVM_L2_CNTL4, tmp); in gfxhub_v1_0_init_cache_regs()
Dgmc_v8_0.c887 tmp = RREG32(mmVM_L2_CNTL4); in gmc_v8_0_gart_enable()
900 WREG32(mmVM_L2_CNTL4, tmp); in gmc_v8_0_gart_enable()
Dmmhub_v1_0.c196 WREG32_SOC15(MMHUB, 0, mmVM_L2_CNTL4, tmp); in mmhub_v1_0_init_cache_regs()
/drivers/gpu/drm/amd/include/asic_reg/gmc/
Dgmc_8_2_d.h657 #define mmVM_L2_CNTL4 0x578 macro
Dgmc_8_1_d.h655 #define mmVM_L2_CNTL4 0x578 macro
/drivers/gpu/drm/amd/include/asic_reg/mmhub/
Dmmhub_1_0_offset.h1308 #define mmVM_L2_CNTL4 … macro
Dmmhub_9_1_offset.h1340 #define mmVM_L2_CNTL4 … macro
Dmmhub_9_3_0_offset.h1324 #define mmVM_L2_CNTL4 … macro
/drivers/gpu/drm/amd/include/asic_reg/gc/
Dgc_9_0_offset.h1209 #define mmVM_L2_CNTL4 … macro
Dgc_9_2_1_offset.h1173 #define mmVM_L2_CNTL4 … macro
Dgc_9_1_offset.h1235 #define mmVM_L2_CNTL4 … macro