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Searched refs:num_clk (Results 1 – 8 of 8) sorted by relevance

/drivers/gpu/drm/msm/disp/dpu1/
Ddpu_io_util.c16 void msm_dss_put_clk(struct dss_clk *clk_arry, int num_clk) in msm_dss_put_clk() argument
20 for (i = num_clk - 1; i >= 0; i--) { in msm_dss_put_clk()
27 int msm_dss_get_clk(struct device *dev, struct dss_clk *clk_arry, int num_clk) in msm_dss_get_clk() argument
31 for (i = 0; i < num_clk; i++) { in msm_dss_get_clk()
54 int msm_dss_clk_set_rate(struct dss_clk *clk_arry, int num_clk) in msm_dss_clk_set_rate() argument
58 for (i = 0; i < num_clk; i++) { in msm_dss_clk_set_rate()
87 int msm_dss_enable_clk(struct dss_clk *clk_arry, int num_clk, int enable) in msm_dss_enable_clk() argument
92 for (i = 0; i < num_clk; i++) { in msm_dss_enable_clk()
110 for (i = num_clk - 1; i >= 0; i--) { in msm_dss_enable_clk()
127 int num_clk = 0; in msm_dss_parse_clock() local
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Ddpu_io_util.h30 unsigned int num_clk; member
34 int msm_dss_get_clk(struct device *dev, struct dss_clk *clk_arry, int num_clk);
35 void msm_dss_put_clk(struct dss_clk *clk_arry, int num_clk);
36 int msm_dss_clk_set_rate(struct dss_clk *clk_arry, int num_clk);
37 int msm_dss_enable_clk(struct dss_clk *clk_arry, int num_clk, int enable);
Ddpu_mdss.c149 ret = msm_dss_enable_clk(mp->clk_config, mp->num_clk, true); in dpu_mdss_enable()
184 ret = msm_dss_enable_clk(mp->clk_config, mp->num_clk, false); in dpu_mdss_disable()
204 msm_dss_put_clk(mp->clk_config, mp->num_clk); in dpu_mdss_destroy()
270 msm_dss_put_clk(mp->clk_config, mp->num_clk); in dpu_mdss_init()
Ddpu_kms.c871 for (i = 0; i < mp->num_clk; i++) { in _dpu_kms_get_clk()
1140 msm_dss_put_clk(mp->clk_config, mp->num_clk); in dpu_unbind()
1142 mp->num_clk = 0; in dpu_unbind()
1177 rc = msm_dss_enable_clk(mp->clk_config, mp->num_clk, false); in dpu_runtime_suspend()
1204 rc = msm_dss_enable_clk(mp->clk_config, mp->num_clk, true); in dpu_runtime_resume()
/drivers/gpu/drm/msm/dp/
Ddp_parser.c111 int num_clk, i, rc; in dp_parser_init_clk_data() local
119 num_clk = of_property_count_strings(dev->of_node, "clock-names"); in dp_parser_init_clk_data()
120 if (num_clk <= 0) { in dp_parser_init_clk_data()
125 for (i = 0; i < num_clk; i++) { in dp_parser_init_clk_data()
147 core_power->num_clk = core_clk_count; in dp_parser_init_clk_data()
149 sizeof(struct dss_clk) * core_power->num_clk, in dp_parser_init_clk_data()
160 ctrl_power->num_clk = ctrl_clk_count; in dp_parser_init_clk_data()
162 sizeof(struct dss_clk) * ctrl_power->num_clk, in dp_parser_init_clk_data()
165 ctrl_power->num_clk = 0; in dp_parser_init_clk_data()
175 stream_power->num_clk = stream_clk_count; in dp_parser_init_clk_data()
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Ddp_power.c106 rc = msm_dss_get_clk(dev, core->clk_config, core->num_clk); in dp_power_clk_init()
113 rc = msm_dss_get_clk(dev, ctrl->clk_config, ctrl->num_clk); in dp_power_clk_init()
117 msm_dss_put_clk(core->clk_config, core->num_clk); in dp_power_clk_init()
121 rc = msm_dss_get_clk(dev, stream->clk_config, stream->num_clk); in dp_power_clk_init()
125 msm_dss_put_clk(core->clk_config, core->num_clk); in dp_power_clk_init()
145 msm_dss_put_clk(ctrl->clk_config, ctrl->num_clk); in dp_power_clk_deinit()
146 msm_dss_put_clk(core->clk_config, core->num_clk); in dp_power_clk_deinit()
147 msm_dss_put_clk(stream->clk_config, stream->num_clk); in dp_power_clk_deinit()
158 rc = msm_dss_clk_set_rate(mp->clk_config, mp->num_clk); in dp_power_clk_set_rate()
165 rc = msm_dss_enable_clk(mp->clk_config, mp->num_clk, enable); in dp_power_clk_set_rate()
Ddp_ctrl.c1302 u32 num = ctrl->parser->mp[module].num_clk; in dp_ctrl_set_clock_rate()
/drivers/gpu/drm/exynos/
Dexynos_drm_scaler.c34 unsigned int num_clk; member
515 for (i = 0; i < scaler->scaler_data->num_clk; ++i) { in scaler_probe()
567 for (i = 0; i < scaler->scaler_data->num_clk; ++i) in scaler_clk_ctrl()
703 .num_clk = 1,
710 .num_clk = 3,