Home
last modified time | relevance | path

Searched refs:num_levels (Results 1 – 25 of 43) sorted by relevance

12

/drivers/gpu/drm/amd/display/amdgpu_dm/
Damdgpu_dm_pp_smu.c131 clks->num_levels = 6; in get_default_clock_levels()
136 clks->num_levels = 6; in get_default_clock_levels()
141 clks->num_levels = 2; in get_default_clock_levels()
146 clks->num_levels = 0; in get_default_clock_levels()
263 dc_clks->num_levels = DM_PP_MAX_CLOCK_LEVELS; in pp_to_dc_clock_levels()
265 dc_clks->num_levels = pp_clks->count; in pp_to_dc_clock_levels()
270 for (i = 0; i < dc_clks->num_levels; i++) { in pp_to_dc_clock_levels()
283 if (pp_clks->num_levels > DM_PP_MAX_CLOCK_LEVELS) { in pp_to_dc_clock_levels_with_latency()
286 pp_clks->num_levels, in pp_to_dc_clock_levels_with_latency()
289 clk_level_info->num_levels = DM_PP_MAX_CLOCK_LEVELS; in pp_to_dc_clock_levels_with_latency()
[all …]
/drivers/firmware/arm_scmi/
Dvoltage.c87 u32 num_levels; in scmi_init_voltage_levels() local
89 num_levels = num_returned + num_remaining; in scmi_init_voltage_levels()
94 if (!num_levels || in scmi_init_voltage_levels()
98 num_levels, num_returned, num_remaining, v->id); in scmi_init_voltage_levels()
102 v->levels_uv = devm_kcalloc(dev, num_levels, sizeof(u32), GFP_KERNEL); in scmi_init_voltage_levels()
106 v->num_levels = num_levels; in scmi_init_voltage_levels()
168 if (!v->num_levels) { in scmi_voltage_descriptors_get()
177 if (desc_index + num_returned > v->num_levels) { in scmi_voltage_descriptors_get()
180 v->num_levels); in scmi_voltage_descriptors_get()
202 v->num_levels = 0; in scmi_voltage_descriptors_get()
[all …]
/drivers/video/backlight/
Dled_bl.c127 int num_levels; in led_bl_parse_levels() local
134 num_levels = of_property_count_u32_elems(node, "brightness-levels"); in led_bl_parse_levels()
135 if (num_levels > 1) { in led_bl_parse_levels()
140 levels = devm_kzalloc(dev, sizeof(u32) * num_levels, in led_bl_parse_levels()
147 num_levels); in led_bl_parse_levels()
156 for (i = 0 ; i < num_levels; i++) { in led_bl_parse_levels()
161 priv->max_brightness = num_levels - 1; in led_bl_parse_levels()
163 } else if (num_levels >= 0) in led_bl_parse_levels()
Dpwm_bl.c233 unsigned int num_levels = 0; in pwm_backlight_parse_dt() local
314 num_levels += num_steps; in pwm_backlight_parse_dt()
316 num_levels++; in pwm_backlight_parse_dt()
318 num_levels++; in pwm_backlight_parse_dt()
320 num_levels); in pwm_backlight_parse_dt()
326 size = sizeof(*table) * num_levels; in pwm_backlight_parse_dt()
361 data->max_brightness = num_levels; in pwm_backlight_parse_dt()
/drivers/gpu/drm/amd/display/dc/dce112/
Ddce112_resource.c1090 clks.clocks_in_khz[clks.num_levels-1], 1000); in bw_calcs_data_update_from_pplib()
1092 clks.clocks_in_khz[clks.num_levels/8], 1000); in bw_calcs_data_update_from_pplib()
1094 clks.clocks_in_khz[clks.num_levels*2/8], 1000); in bw_calcs_data_update_from_pplib()
1096 clks.clocks_in_khz[clks.num_levels*3/8], 1000); in bw_calcs_data_update_from_pplib()
1098 clks.clocks_in_khz[clks.num_levels*4/8], 1000); in bw_calcs_data_update_from_pplib()
1100 clks.clocks_in_khz[clks.num_levels*5/8], 1000); in bw_calcs_data_update_from_pplib()
1102 clks.clocks_in_khz[clks.num_levels*6/8], 1000); in bw_calcs_data_update_from_pplib()
1115 clks.clocks_in_khz[clks.num_levels>>1] * memory_type_multiplier, in bw_calcs_data_update_from_pplib()
1118 clks.clocks_in_khz[clks.num_levels-1] * memory_type_multiplier, in bw_calcs_data_update_from_pplib()
1126 eng_clks.data[eng_clks.num_levels-1].clocks_in_khz, 1000); in bw_calcs_data_update_from_pplib()
[all …]
/drivers/gpu/drm/amd/display/dc/dce120/
Ddce120_resource.c936 &eng_clks) || eng_clks.num_levels == 0) { in bw_calcs_data_update_from_pplib()
938 eng_clks.num_levels = 8; in bw_calcs_data_update_from_pplib()
941 for (i = 0; i < eng_clks.num_levels; i++) { in bw_calcs_data_update_from_pplib()
949 eng_clks.data[eng_clks.num_levels-1].clocks_in_khz, 1000); in bw_calcs_data_update_from_pplib()
951 eng_clks.data[eng_clks.num_levels/8].clocks_in_khz, 1000); in bw_calcs_data_update_from_pplib()
953 eng_clks.data[eng_clks.num_levels*2/8].clocks_in_khz, 1000); in bw_calcs_data_update_from_pplib()
955 eng_clks.data[eng_clks.num_levels*3/8].clocks_in_khz, 1000); in bw_calcs_data_update_from_pplib()
957 eng_clks.data[eng_clks.num_levels*4/8].clocks_in_khz, 1000); in bw_calcs_data_update_from_pplib()
959 eng_clks.data[eng_clks.num_levels*5/8].clocks_in_khz, 1000); in bw_calcs_data_update_from_pplib()
961 eng_clks.data[eng_clks.num_levels*6/8].clocks_in_khz, 1000); in bw_calcs_data_update_from_pplib()
[all …]
/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn30/
Ddcn30_clk_mgr.c86 …ock(struct clk_mgr_internal *clk_mgr, PPCLK_e clk, unsigned int *entry_0, unsigned int *num_levels) in dcn3_init_single_clock() argument
94 *num_levels = 2; in dcn3_init_single_clock()
98 *num_levels = ret & 0xFF; in dcn3_init_single_clock()
101 for (i = 0; i < *num_levels; i++) { in dcn3_init_single_clock()
153 unsigned int num_levels; in dcn3_init_clocks() local
176 &num_levels); in dcn3_init_clocks()
181 &num_levels); in dcn3_init_clocks()
188 &num_levels); in dcn3_init_clocks()
193 &num_levels); in dcn3_init_clocks()
198 &num_levels); in dcn3_init_clocks()
[all …]
/drivers/gpu/drm/radeon/
Dsumo_dpm.c347 u32 highest_engine_clock = ps->levels[ps->num_levels - 1].sclk; in sumo_program_bsp()
354 for (i = 0; i < ps->num_levels - 1; i++) in sumo_program_bsp()
408 for (i = 0; i < ps->num_levels; i++) { in sumo_program_at()
409 asi = (i == ps->num_levels - 1) ? pi->pasi : pi->asi; in sumo_program_at()
423 a_t = CG_R(m_a * r[ps->num_levels - 1] / 100) | in sumo_program_at()
424 CG_L(m_a * l[ps->num_levels - 1] / 100); in sumo_program_at()
670 pi->boost_pl = new_ps->levels[new_ps->num_levels - 1]; in sumo_patch_boost_state()
743 dpm_ctrl4 |= (1 << (new_ps->num_levels - 1)); in sumo_program_wl()
759 u32 n_current_state_levels = (old_ps == NULL) ? 1 : old_ps->num_levels; in sumo_program_power_levels_0_to_n()
761 for (i = 0; i < new_ps->num_levels; i++) { in sumo_program_power_levels_0_to_n()
[all …]
Dtrinity_dpm.c846 u32 n_current_state_levels = (old_ps == NULL) ? 1 : old_ps->num_levels; in trinity_program_power_levels_0_to_n()
848 for (i = 0; i < new_ps->num_levels; i++) { in trinity_program_power_levels_0_to_n()
853 for (i = new_ps->num_levels; i < n_current_state_levels; i++) in trinity_program_power_levels_0_to_n()
969 if (new_ps->levels[new_ps->num_levels - 1].sclk >= in trinity_set_uvd_clock_before_set_eng_clock()
970 current_ps->levels[current_ps->num_levels - 1].sclk) in trinity_set_uvd_clock_before_set_eng_clock()
983 if (new_ps->levels[new_ps->num_levels - 1].sclk < in trinity_set_uvd_clock_after_set_eng_clock()
984 current_ps->levels[current_ps->num_levels - 1].sclk) in trinity_set_uvd_clock_after_set_eng_clock()
1209 if (ps->num_levels <= 1) in trinity_dpm_force_performance_level()
1216 ret = trinity_dpm_n_levels_disabled(rdev, ps->num_levels - 1); in trinity_dpm_force_performance_level()
1220 for (i = 0; i < ps->num_levels; i++) { in trinity_dpm_force_performance_level()
[all …]
Dr100_track.h44 unsigned num_levels; member
Dkv_dpm.c1725 if (table->entries[i].clk <= new_ps->levels[new_ps->num_levels - 1].sclk) in kv_set_valid_clock_range()
1732 (table->entries[pi->lowest_valid].clk - new_ps->levels[new_ps->num_levels - 1].sclk)) in kv_set_valid_clock_range()
1751 new_ps->levels[new_ps->num_levels - 1].sclk) in kv_set_valid_clock_range()
1760 new_ps->levels[new_ps->num_levels -1].sclk)) in kv_set_valid_clock_range()
2188 for (i = 0; i < ps->num_levels; i++) { in kv_apply_state_adjust_rules()
2194 for (i = 0; i < ps->num_levels; i++) { in kv_apply_state_adjust_rules()
2206 for (i = 0; i < ps->num_levels; i++) { in kv_apply_state_adjust_rules()
2217 for (i = 0; i < ps->num_levels; i++) { in kv_apply_state_adjust_rules()
2579 ps->num_levels = 1; in kv_patch_boot_state()
2624 ps->num_levels = index + 1; in kv_parse_pplib_clock_info()
[all …]
Dtrinity_dpm.h48 u32 num_levels; member
Dkv_dpm.h83 u32 num_levels; member
/drivers/gpu/drm/amd/display/dc/
Ddm_services_types.h98 uint32_t num_levels; member
108 uint32_t num_levels; member
118 uint32_t num_levels; member
/drivers/gpu/drm/amd/include/
Ddm_pp_interface.h175 uint32_t num_levels; member
185 uint32_t num_levels; member
/drivers/gpu/drm/amd/display/dc/dce110/
Ddce110_resource.c1298 clks.clocks_in_khz[clks.num_levels-1], 1000); in bw_calcs_data_update_from_pplib()
1300 clks.clocks_in_khz[clks.num_levels/8], 1000); in bw_calcs_data_update_from_pplib()
1302 clks.clocks_in_khz[clks.num_levels*2/8], 1000); in bw_calcs_data_update_from_pplib()
1304 clks.clocks_in_khz[clks.num_levels*3/8], 1000); in bw_calcs_data_update_from_pplib()
1306 clks.clocks_in_khz[clks.num_levels*4/8], 1000); in bw_calcs_data_update_from_pplib()
1308 clks.clocks_in_khz[clks.num_levels*5/8], 1000); in bw_calcs_data_update_from_pplib()
1310 clks.clocks_in_khz[clks.num_levels*6/8], 1000); in bw_calcs_data_update_from_pplib()
1321 clks.clocks_in_khz[clks.num_levels-1], 1000); in bw_calcs_data_update_from_pplib()
1323 clks.clocks_in_khz[clks.num_levels>>1], 1000); in bw_calcs_data_update_from_pplib()
1336 clks.clocks_in_khz[clks.num_levels>>1] * MEMORY_TYPE_MULTIPLIER_CZ, in bw_calcs_data_update_from_pplib()
[all …]
/drivers/gpu/drm/amd/display/dc/clk_mgr/dce110/
Ddce110_clk_mgr.c76 if (dc->sclk_lvls.num_levels == 0) in determine_sclk_from_bounding_box()
79 for (i = 0; i < dc->sclk_lvls.num_levels; i++) { in determine_sclk_from_bounding_box()
89 return dc->sclk_lvls.clocks_in_khz[dc->sclk_lvls.num_levels - 1]; in determine_sclk_from_bounding_box()
/drivers/gpu/drm/amd/pm/powerplay/hwmgr/
Dsmu10_hwmgr.c1107 clocks->num_levels = 0; in smu10_get_clock_by_type_with_latency()
1110 clocks->data[clocks->num_levels].clocks_in_khz = in smu10_get_clock_by_type_with_latency()
1112 clocks->data[clocks->num_levels].latency_in_us = latency_required ? in smu10_get_clock_by_type_with_latency()
1116 clocks->num_levels++; in smu10_get_clock_by_type_with_latency()
1161 clocks->num_levels = 0; in smu10_get_clock_by_type_with_voltage()
1164 clocks->data[clocks->num_levels].clocks_in_khz = pclk_vol_table->entries[i].clk * 10; in smu10_get_clock_by_type_with_voltage()
1165 clocks->data[clocks->num_levels].voltage_in_mv = pclk_vol_table->entries[i].vol; in smu10_get_clock_by_type_with_voltage()
1166 clocks->num_levels++; in smu10_get_clock_by_type_with_voltage()
Dvega12_hwmgr.c1847 clocks->num_levels = ucount; in vega12_get_sclks()
1880 clocks->num_levels = data->mclk_latency_table.count = ucount; in vega12_get_memclocks()
1908 clocks->num_levels = ucount; in vega12_get_dcefclocks()
1936 clocks->num_levels = ucount; in vega12_get_socclocks()
1972 clocks->num_levels = 0; in vega12_get_clock_by_type_with_voltage()
2259 for (i = 0; i < clocks.num_levels; i++) in vega12_print_clock_levels()
2275 for (i = 0; i < clocks.num_levels; i++) in vega12_print_clock_levels()
2293 for (i = 0; i < clocks.num_levels; i++) in vega12_print_clock_levels()
2311 for (i = 0; i < clocks.num_levels; i++) in vega12_print_clock_levels()
/drivers/gpu/drm/i915/display/
Dintel_display_debugfs.c1439 int num_levels; in wm_latency_show() local
1442 num_levels = 3; in wm_latency_show()
1444 num_levels = 1; in wm_latency_show()
1446 num_levels = 3; in wm_latency_show()
1448 num_levels = ilk_wm_max_level(dev_priv) + 1; in wm_latency_show()
1452 for (level = 0; level < num_levels; level++) { in wm_latency_show()
1556 int num_levels; in wm_latency_write() local
1562 num_levels = 3; in wm_latency_write()
1564 num_levels = 1; in wm_latency_write()
1566 num_levels = 3; in wm_latency_write()
[all …]
/drivers/gpu/drm/amd/display/dc/calcs/
Ddcn_calcs.c1473 if (clks->num_levels == 0) in verify_clock_values()
1476 for (i = 0; i < clks->num_levels; i++) in verify_clock_values()
1501 ASSERT(fclks.num_levels); in dcn_bw_update_from_pplib()
1504 vmid0p72_idx = fclks.num_levels - in dcn_bw_update_from_pplib()
1505 (fclks.num_levels > 2 ? 3 : (fclks.num_levels > 1 ? 2 : 1)); in dcn_bw_update_from_pplib()
1506 vnom0p8_idx = fclks.num_levels - (fclks.num_levels > 1 ? 2 : 1); in dcn_bw_update_from_pplib()
1507 vmax0p9_idx = fclks.num_levels - 1; in dcn_bw_update_from_pplib()
1536 if (res && dcfclks.num_levels >= 3) { in dcn_bw_update_from_pplib()
1538 dc->dcn_soc->dcfclkv_mid0p72 = dcfclks.data[dcfclks.num_levels - 3].clocks_in_khz / 1000.0; in dcn_bw_update_from_pplib()
1539 dc->dcn_soc->dcfclkv_nom0p8 = dcfclks.data[dcfclks.num_levels - 2].clocks_in_khz / 1000.0; in dcn_bw_update_from_pplib()
[all …]
/drivers/net/ethernet/mellanox/mlx5/core/
Dfs_core.c51 .num_levels = num_levels_val,\
146 int num_levels; member
1149 if (ft_attr->level >= fs_prio->num_levels) { in __mlx5_create_flow_table()
2353 int num_levels, in _fs_create_prio() argument
2365 fs_prio->num_levels = num_levels; in _fs_create_prio()
2374 int num_levels) in fs_create_prio_chained() argument
2376 return _fs_create_prio(ns, prio, num_levels, FS_TYPE_PRIO_CHAINS); in fs_create_prio_chained()
2380 unsigned int prio, int num_levels) in fs_create_prio() argument
2382 return _fs_create_prio(ns, prio, num_levels, FS_TYPE_PRIO); in fs_create_prio()
2418 fs_prio = fs_create_prio(ns, prio++, prio_metadata->num_levels); in create_leaf_prios()
[all …]
/drivers/gpu/drm/amd/pm/powerplay/
Dkv_dpm.c1778 if (table->entries[i].clk <= new_ps->levels[new_ps->num_levels - 1].sclk) in kv_set_valid_clock_range()
1785 (table->entries[pi->lowest_valid].clk - new_ps->levels[new_ps->num_levels - 1].sclk)) in kv_set_valid_clock_range()
1804 new_ps->levels[new_ps->num_levels - 1].sclk) in kv_set_valid_clock_range()
1813 new_ps->levels[new_ps->num_levels -1].sclk)) in kv_set_valid_clock_range()
2242 for (i = 0; i < ps->num_levels; i++) { in kv_apply_state_adjust_rules()
2248 for (i = 0; i < ps->num_levels; i++) { in kv_apply_state_adjust_rules()
2260 for (i = 0; i < ps->num_levels; i++) { in kv_apply_state_adjust_rules()
2271 for (i = 0; i < ps->num_levels; i++) { in kv_apply_state_adjust_rules()
2636 ps->num_levels = 1; in kv_patch_boot_state()
2681 ps->num_levels = index + 1; in kv_parse_pplib_clock_info()
[all …]
/drivers/hwmon/
Daspeed-pwm-tacho.c812 u32 pwm_port, u8 num_levels) in aspeed_create_pwm_cooling() argument
822 cdev->cooling_levels = devm_kzalloc(dev, num_levels, GFP_KERNEL); in aspeed_create_pwm_cooling()
826 cdev->max_state = num_levels - 1; in aspeed_create_pwm_cooling()
829 num_levels); in aspeed_create_pwm_cooling()
Dnpcm750-pwm-fan.c825 u32 pwm_port, u8 num_levels) in npcm7xx_create_pwm_cooling() argument
834 cdev->cooling_levels = devm_kzalloc(dev, num_levels, GFP_KERNEL); in npcm7xx_create_pwm_cooling()
838 cdev->max_state = num_levels - 1; in npcm7xx_create_pwm_cooling()
841 num_levels); in npcm7xx_create_pwm_cooling()

12