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Searched refs:num_rxq (Results 1 – 17 of 17) sorted by relevance

/drivers/net/ethernet/intel/ice/
Dice_xsk.c157 if (q_idx >= vsi->num_rxq || q_idx >= vsi->num_txq) in ice_qp_dis()
214 if (q_idx >= vsi->num_rxq || q_idx >= vsi->num_txq) in ice_qp_ena()
339 vsi->num_xsk_pools = min_t(u16, vsi->num_rxq, vsi->num_txq); in ice_xsk_pool_enable()
374 if (qid >= vsi->num_rxq || qid >= vsi->num_txq) { in ice_xsk_pool_setup()
Dice_lib.c47 for (i = 0; i < vsi->num_rxq; i++) in ice_vsi_ctrl_all_rx_rings()
52 for (i = 0; i < vsi->num_rxq; i++) { in ice_vsi_ctrl_all_rx_rings()
188 vsi->num_rxq = vsi->req_rxq; in ice_vsi_set_num_qs()
832 vsi->num_rxq = offset; in ice_vsi_setup_q_map()
834 vsi->num_rxq = qcount_rx; in ice_vsi_setup_q_map()
838 if (vsi->type == ICE_VSI_VF && vsi->num_txq != vsi->num_rxq) { in ice_vsi_setup_q_map()
843 vsi->num_txq = vsi->num_rxq; in ice_vsi_setup_q_map()
853 ctxt->info.q_mapping[1] = cpu_to_le16(vsi->num_rxq); in ice_vsi_setup_q_map()
1342 vsi->rss_size = min_t(u16, vsi->rss_size, vsi->num_rxq); in ice_vsi_cfg_rss_lut_key()
1695 for (i = 0; i < vsi->num_rxq; i++) { in ice_vsi_cfg_rxqs()
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Dice.h114 for ((i) = 0; (i) < (vsi)->num_rxq; (i)++)
319 u16 num_rxq; /* Used Rx queues */ member
Dice_virtchnl_pf.c929 u16 num_msix_per_vf, num_txq, num_rxq; in ice_set_per_vf_res() local
960 num_rxq = ice_determine_res(pf, ice_get_avail_rxq_count(pf), in ice_set_per_vf_res()
966 if (!num_txq || !num_rxq) { in ice_set_per_vf_res()
979 pf->num_qps_per_vf = min_t(int, num_txq, num_rxq); in ice_set_per_vf_res()
2935 u16 num_rxq = 0, num_txq = 0; in ice_vc_cfg_qs_msg() local
2987 num_rxq++; in ice_vc_cfg_qs_msg()
3018 vsi->num_rxq = num_rxq; in ice_vc_cfg_qs_msg()
3021 vsi->tc_cfg.tc_info[0].qcount_rx = num_rxq; in ice_vc_cfg_qs_msg()
Dice_ethtool.c2861 rx_rings = kcalloc(vsi->num_rxq, sizeof(*rx_rings), GFP_KERNEL); in ice_set_ringparam()
3270 (u16)pf->hw.func_caps.common_cap.num_rxq); in ice_get_max_rxq()
3314 ch->rx_count = vsi->num_rxq - ch->combined_count; in ice_get_channels()
3415 if (ch->rx_count == vsi->num_rxq - curr_combined) in ice_set_channels()
3559 if (q_num < vsi->num_rxq && q_num < vsi->num_txq) { in ice_get_q_coalesce()
3566 } else if (q_num < vsi->num_rxq) { in ice_get_q_coalesce()
3714 if (q_num < vsi->num_rxq && q_num < vsi->num_txq) { in ice_set_q_coalesce()
3724 } else if (q_num < vsi->num_rxq) { in ice_set_q_coalesce()
3800 if (v_idx >= vsi->num_rxq && v_idx >= vsi->num_txq) in __ice_set_coalesce()
Dice_base.c574 rx_rings_rem = vsi->num_rxq; in ice_vsi_map_rings_to_vectors()
604 q_base = vsi->num_rxq - rx_rings_rem; in ice_vsi_map_rings_to_vectors()
Dice_type.h227 u16 num_rxq; /* Number/Total Rx queues */ member
Dice_common.c1831 caps->num_rxq = number; in ice_parse_common_caps()
1835 caps->num_rxq); in ice_parse_common_caps()
2318 func_caps->common_cap.num_rxq = 1; in ice_set_safe_mode_caps()
2348 dev_caps->common_cap.num_rxq = num_funcs; in ice_set_safe_mode_caps()
Dice_dcb_lib.c207 for (i = 0; i < vsi->num_rxq; i++) { in ice_vsi_cfg_dcb_rings()
Dice_main.c3378 pf->max_pf_rxqs = func_caps->common_cap.num_rxq; in ice_set_pf_caps()
5623 if (!vsi->num_txq || !vsi->num_rxq) in ice_get_stats64()
5769 if (!vsi->num_rxq) { in ice_vsi_setup_rx_rings()
5884 err = netif_set_real_num_rx_queues(vsi->netdev, vsi->num_rxq); in ice_vsi_open()
Dice_ethtool_fdir.c1499 if (ring >= vsi->num_rxq) in ice_set_fdir_input_set()
/drivers/net/ethernet/atheros/alx/
Dalx.h122 int num_rxq; member
Dmain.c832 int err, num_vec, num_txq, num_rxq; in alx_enable_msix() local
835 num_rxq = 1; in alx_enable_msix()
836 num_vec = max_t(int, num_txq, num_rxq) + 1; in alx_enable_msix()
848 alx->num_rxq = num_rxq; in alx_enable_msix()
912 alx->num_rxq = 1; in alx_init_intr()
1229 netif_set_real_num_rx_queues(alx->dev, alx->num_rxq); in __alx_open()
/drivers/net/ethernet/stmicro/stmmac/
Ddwmac5.h114 void dwmac5_fpe_configure(void __iomem *ioaddr, u32 num_txq, u32 num_rxq,
Ddwmac5.c606 void dwmac5_fpe_configure(void __iomem *ioaddr, u32 num_txq, u32 num_rxq, in dwmac5_fpe_configure() argument
622 value |= (num_rxq - 1) << GMAC_RXQCTRL_FPRQ_SHIFT; in dwmac5_fpe_configure()
Ddwxgmac2_core.c525 struct stmmac_rss *cfg, u32 num_rxq) in dwxgmac2_rss_configure() argument
551 for (i = 0; i < num_rxq; i++) in dwxgmac2_rss_configure()
1498 u32 num_rxq, bool enable) in dwxgmac3_fpe_configure() argument
1513 value |= (num_rxq - 1) << XGMAC_RQ_SHIFT; in dwxgmac3_fpe_configure()
Dhwif.h368 struct stmmac_rss *cfg, u32 num_rxq);
395 void (*fpe_configure)(void __iomem *ioaddr, u32 num_txq, u32 num_rxq,