Home
last modified time | relevance | path

Searched refs:nvkm_wo32 (Results 1 – 25 of 54) sorted by relevance

123

/drivers/gpu/drm/nouveau/nvkm/engine/gr/
Dnv25.c42 nvkm_wo32(chan->inst, 0x0028, 0x00000001 | (chan->chid << 24)); in nv25_gr_chan_new()
43 nvkm_wo32(chan->inst, 0x035c, 0xffff0000); in nv25_gr_chan_new()
44 nvkm_wo32(chan->inst, 0x03c0, 0x0fff0000); in nv25_gr_chan_new()
45 nvkm_wo32(chan->inst, 0x03c4, 0x0fff0000); in nv25_gr_chan_new()
46 nvkm_wo32(chan->inst, 0x049c, 0x00000101); in nv25_gr_chan_new()
47 nvkm_wo32(chan->inst, 0x04b0, 0x00000111); in nv25_gr_chan_new()
48 nvkm_wo32(chan->inst, 0x04c8, 0x00000080); in nv25_gr_chan_new()
49 nvkm_wo32(chan->inst, 0x04cc, 0xffff0000); in nv25_gr_chan_new()
50 nvkm_wo32(chan->inst, 0x04d0, 0x00000001); in nv25_gr_chan_new()
51 nvkm_wo32(chan->inst, 0x04e4, 0x44400000); in nv25_gr_chan_new()
[all …]
Dnv35.c42 nvkm_wo32(chan->inst, 0x0028, 0x00000001 | (chan->chid << 24)); in nv35_gr_chan_new()
43 nvkm_wo32(chan->inst, 0x040c, 0x00000101); in nv35_gr_chan_new()
44 nvkm_wo32(chan->inst, 0x0420, 0x00000111); in nv35_gr_chan_new()
45 nvkm_wo32(chan->inst, 0x0424, 0x00000060); in nv35_gr_chan_new()
46 nvkm_wo32(chan->inst, 0x0440, 0x00000080); in nv35_gr_chan_new()
47 nvkm_wo32(chan->inst, 0x0444, 0xffff0000); in nv35_gr_chan_new()
48 nvkm_wo32(chan->inst, 0x0448, 0x00000001); in nv35_gr_chan_new()
49 nvkm_wo32(chan->inst, 0x045c, 0x44400000); in nv35_gr_chan_new()
50 nvkm_wo32(chan->inst, 0x0488, 0xffff0000); in nv35_gr_chan_new()
52 nvkm_wo32(chan->inst, i, 0x0fff0000); in nv35_gr_chan_new()
[all …]
Dnv34.c42 nvkm_wo32(chan->inst, 0x0028, 0x00000001 | (chan->chid << 24)); in nv34_gr_chan_new()
43 nvkm_wo32(chan->inst, 0x040c, 0x01000101); in nv34_gr_chan_new()
44 nvkm_wo32(chan->inst, 0x0420, 0x00000111); in nv34_gr_chan_new()
45 nvkm_wo32(chan->inst, 0x0424, 0x00000060); in nv34_gr_chan_new()
46 nvkm_wo32(chan->inst, 0x0440, 0x00000080); in nv34_gr_chan_new()
47 nvkm_wo32(chan->inst, 0x0444, 0xffff0000); in nv34_gr_chan_new()
48 nvkm_wo32(chan->inst, 0x0448, 0x00000001); in nv34_gr_chan_new()
49 nvkm_wo32(chan->inst, 0x045c, 0x44400000); in nv34_gr_chan_new()
50 nvkm_wo32(chan->inst, 0x0480, 0xffff0000); in nv34_gr_chan_new()
52 nvkm_wo32(chan->inst, i, 0x0fff0000); in nv34_gr_chan_new()
[all …]
Dnv2a.c42 nvkm_wo32(chan->inst, 0x0000, 0x00000001 | (chan->chid << 24)); in nv2a_gr_chan_new()
43 nvkm_wo32(chan->inst, 0x033c, 0xffff0000); in nv2a_gr_chan_new()
44 nvkm_wo32(chan->inst, 0x03a0, 0x0fff0000); in nv2a_gr_chan_new()
45 nvkm_wo32(chan->inst, 0x03a4, 0x0fff0000); in nv2a_gr_chan_new()
46 nvkm_wo32(chan->inst, 0x047c, 0x00000101); in nv2a_gr_chan_new()
47 nvkm_wo32(chan->inst, 0x0490, 0x00000111); in nv2a_gr_chan_new()
48 nvkm_wo32(chan->inst, 0x04a8, 0x44400000); in nv2a_gr_chan_new()
50 nvkm_wo32(chan->inst, i, 0x00030303); in nv2a_gr_chan_new()
52 nvkm_wo32(chan->inst, i, 0x00080000); in nv2a_gr_chan_new()
54 nvkm_wo32(chan->inst, i, 0x01012000); in nv2a_gr_chan_new()
[all …]
Dnv30.c43 nvkm_wo32(chan->inst, 0x0028, 0x00000001 | (chan->chid << 24)); in nv30_gr_chan_new()
44 nvkm_wo32(chan->inst, 0x0410, 0x00000101); in nv30_gr_chan_new()
45 nvkm_wo32(chan->inst, 0x0424, 0x00000111); in nv30_gr_chan_new()
46 nvkm_wo32(chan->inst, 0x0428, 0x00000060); in nv30_gr_chan_new()
47 nvkm_wo32(chan->inst, 0x0444, 0x00000080); in nv30_gr_chan_new()
48 nvkm_wo32(chan->inst, 0x0448, 0xffff0000); in nv30_gr_chan_new()
49 nvkm_wo32(chan->inst, 0x044c, 0x00000001); in nv30_gr_chan_new()
50 nvkm_wo32(chan->inst, 0x0460, 0x44400000); in nv30_gr_chan_new()
51 nvkm_wo32(chan->inst, 0x048c, 0xffff0000); in nv30_gr_chan_new()
53 nvkm_wo32(chan->inst, i, 0x0fff0000); in nv30_gr_chan_new()
[all …]
Dnv20.c24 nvkm_wo32(gr->ctxtab, chan->chid * 4, inst >> 4); in nv20_gr_chan_init()
54 nvkm_wo32(gr->ctxtab, chan->chid * 4, 0x00000000); in nv20_gr_chan_fini()
96 nvkm_wo32(chan->inst, 0x0000, 0x00000001 | (chan->chid << 24)); in nv20_gr_chan_new()
97 nvkm_wo32(chan->inst, 0x033c, 0xffff0000); in nv20_gr_chan_new()
98 nvkm_wo32(chan->inst, 0x03a0, 0x0fff0000); in nv20_gr_chan_new()
99 nvkm_wo32(chan->inst, 0x03a4, 0x0fff0000); in nv20_gr_chan_new()
100 nvkm_wo32(chan->inst, 0x047c, 0x00000101); in nv20_gr_chan_new()
101 nvkm_wo32(chan->inst, 0x0490, 0x00000111); in nv20_gr_chan_new()
102 nvkm_wo32(chan->inst, 0x04a8, 0x44400000); in nv20_gr_chan_new()
104 nvkm_wo32(chan->inst, i, 0x00030303); in nv20_gr_chan_new()
[all …]
/drivers/gpu/drm/nouveau/nvkm/engine/fifo/
Ddmag84.c68 nvkm_wo32(chan->ramfc, 0x08, lower_32_bits(args->v0.offset)); in g84_fifo_dma_new()
69 nvkm_wo32(chan->ramfc, 0x0c, upper_32_bits(args->v0.offset)); in g84_fifo_dma_new()
70 nvkm_wo32(chan->ramfc, 0x10, lower_32_bits(args->v0.offset)); in g84_fifo_dma_new()
71 nvkm_wo32(chan->ramfc, 0x14, upper_32_bits(args->v0.offset)); in g84_fifo_dma_new()
72 nvkm_wo32(chan->ramfc, 0x3c, 0x003f6078); in g84_fifo_dma_new()
73 nvkm_wo32(chan->ramfc, 0x44, 0x01003fff); in g84_fifo_dma_new()
74 nvkm_wo32(chan->ramfc, 0x48, chan->base.push->node->offset >> 4); in g84_fifo_dma_new()
75 nvkm_wo32(chan->ramfc, 0x4c, 0xffffffff); in g84_fifo_dma_new()
76 nvkm_wo32(chan->ramfc, 0x60, 0x7fffffff); in g84_fifo_dma_new()
77 nvkm_wo32(chan->ramfc, 0x78, 0x00000000); in g84_fifo_dma_new()
[all …]
Ddmanv50.c68 nvkm_wo32(chan->ramfc, 0x08, lower_32_bits(args->v0.offset)); in nv50_fifo_dma_new()
69 nvkm_wo32(chan->ramfc, 0x0c, upper_32_bits(args->v0.offset)); in nv50_fifo_dma_new()
70 nvkm_wo32(chan->ramfc, 0x10, lower_32_bits(args->v0.offset)); in nv50_fifo_dma_new()
71 nvkm_wo32(chan->ramfc, 0x14, upper_32_bits(args->v0.offset)); in nv50_fifo_dma_new()
72 nvkm_wo32(chan->ramfc, 0x3c, 0x003f6078); in nv50_fifo_dma_new()
73 nvkm_wo32(chan->ramfc, 0x44, 0x01003fff); in nv50_fifo_dma_new()
74 nvkm_wo32(chan->ramfc, 0x48, chan->base.push->node->offset >> 4); in nv50_fifo_dma_new()
75 nvkm_wo32(chan->ramfc, 0x4c, 0xffffffff); in nv50_fifo_dma_new()
76 nvkm_wo32(chan->ramfc, 0x60, 0x7fffffff); in nv50_fifo_dma_new()
77 nvkm_wo32(chan->ramfc, 0x78, 0x00000000); in nv50_fifo_dma_new()
[all …]
Dgpfifogf100.c97 nvkm_wo32(inst, offset + 0x00, 0x00000000); in gf100_fifo_gpfifo_engine_fini()
98 nvkm_wo32(inst, offset + 0x04, 0x00000000); in gf100_fifo_gpfifo_engine_fini()
116 nvkm_wo32(inst, offset + 0x00, lower_32_bits(addr) | 4); in gf100_fifo_gpfifo_engine_init()
117 nvkm_wo32(inst, offset + 0x04, upper_32_bits(addr)); in gf100_fifo_gpfifo_engine_init()
268 nvkm_wo32(fifo->user.mem, usermem + i, 0x00000000); in gf100_fifo_gpfifo_new()
274 nvkm_wo32(chan->base.inst, 0x08, lower_32_bits(usermem)); in gf100_fifo_gpfifo_new()
275 nvkm_wo32(chan->base.inst, 0x0c, upper_32_bits(usermem)); in gf100_fifo_gpfifo_new()
276 nvkm_wo32(chan->base.inst, 0x10, 0x0000face); in gf100_fifo_gpfifo_new()
277 nvkm_wo32(chan->base.inst, 0x30, 0xfffff902); in gf100_fifo_gpfifo_new()
278 nvkm_wo32(chan->base.inst, 0x48, lower_32_bits(ioffset)); in gf100_fifo_gpfifo_new()
[all …]
Dgpfifog84.c72 nvkm_wo32(chan->ramfc, 0x3c, 0x403f6078); in g84_fifo_gpfifo_new()
73 nvkm_wo32(chan->ramfc, 0x44, 0x01003fff); in g84_fifo_gpfifo_new()
74 nvkm_wo32(chan->ramfc, 0x48, chan->base.push->node->offset >> 4); in g84_fifo_gpfifo_new()
75 nvkm_wo32(chan->ramfc, 0x50, lower_32_bits(ioffset)); in g84_fifo_gpfifo_new()
76 nvkm_wo32(chan->ramfc, 0x54, upper_32_bits(ioffset) | (ilength << 16)); in g84_fifo_gpfifo_new()
77 nvkm_wo32(chan->ramfc, 0x60, 0x7fffffff); in g84_fifo_gpfifo_new()
78 nvkm_wo32(chan->ramfc, 0x78, 0x00000000); in g84_fifo_gpfifo_new()
79 nvkm_wo32(chan->ramfc, 0x7c, 0x30000001); in g84_fifo_gpfifo_new()
80 nvkm_wo32(chan->ramfc, 0x80, ((chan->ramht->bits - 9) << 27) | in g84_fifo_gpfifo_new()
83 nvkm_wo32(chan->ramfc, 0x88, chan->cache->addr >> 10); in g84_fifo_gpfifo_new()
[all …]
Dgpfifogk104.c112 nvkm_wo32(inst, (offset & 0xffff) + 0x00, 0x00000000); in gk104_fifo_gpfifo_engine_fini()
113 nvkm_wo32(inst, (offset & 0xffff) + 0x04, 0x00000000); in gk104_fifo_gpfifo_engine_fini()
115 nvkm_wo32(inst, offset + 0x00, 0x00000000); in gk104_fifo_gpfifo_engine_fini()
116 nvkm_wo32(inst, offset + 0x04, 0x00000000); in gk104_fifo_gpfifo_engine_fini()
137 nvkm_wo32(inst, (offset & 0xffff) + 0x00, datalo); in gk104_fifo_gpfifo_engine_init()
138 nvkm_wo32(inst, (offset & 0xffff) + 0x04, datahi); in gk104_fifo_gpfifo_engine_init()
140 nvkm_wo32(inst, offset + 0x00, datalo); in gk104_fifo_gpfifo_engine_init()
141 nvkm_wo32(inst, offset + 0x04, datahi); in gk104_fifo_gpfifo_engine_init()
303 nvkm_wo32(fifo->user.mem, usermem + i, 0x00000000); in gk104_fifo_gpfifo_new_()
309 nvkm_wo32(chan->base.inst, 0x08, lower_32_bits(usermem)); in gk104_fifo_gpfifo_new_()
[all …]
Dgpfifogv100.c82 nvkm_wo32(inst, 0x0210, 0x00000000); in gv100_fifo_gpfifo_engine_fini()
83 nvkm_wo32(inst, 0x0214, 0x00000000); in gv100_fifo_gpfifo_engine_fini()
102 nvkm_wo32(inst, 0x210, lower_32_bits(addr) | 0x00000004); in gv100_fifo_gpfifo_engine_init()
103 nvkm_wo32(inst, 0x214, upper_32_bits(addr)); in gv100_fifo_gpfifo_engine_init()
183 nvkm_wo32(fifo->user.mem, usermem + i, 0x00000000); in gv100_fifo_gpfifo_new_()
203 nvkm_wo32(chan->base.inst, 0x008, lower_32_bits(usermem)); in gv100_fifo_gpfifo_new_()
204 nvkm_wo32(chan->base.inst, 0x00c, upper_32_bits(usermem)); in gv100_fifo_gpfifo_new_()
205 nvkm_wo32(chan->base.inst, 0x010, 0x0000face); in gv100_fifo_gpfifo_new_()
206 nvkm_wo32(chan->base.inst, 0x030, 0x7ffff902); in gv100_fifo_gpfifo_new_()
207 nvkm_wo32(chan->base.inst, 0x048, lower_32_bits(ioffset)); in gv100_fifo_gpfifo_new_()
[all …]
Dgpfifonv50.c72 nvkm_wo32(chan->ramfc, 0x3c, 0x403f6078); in nv50_fifo_gpfifo_new()
73 nvkm_wo32(chan->ramfc, 0x44, 0x01003fff); in nv50_fifo_gpfifo_new()
74 nvkm_wo32(chan->ramfc, 0x48, chan->base.push->node->offset >> 4); in nv50_fifo_gpfifo_new()
75 nvkm_wo32(chan->ramfc, 0x50, lower_32_bits(ioffset)); in nv50_fifo_gpfifo_new()
76 nvkm_wo32(chan->ramfc, 0x54, upper_32_bits(ioffset) | (ilength << 16)); in nv50_fifo_gpfifo_new()
77 nvkm_wo32(chan->ramfc, 0x60, 0x7fffffff); in nv50_fifo_gpfifo_new()
78 nvkm_wo32(chan->ramfc, 0x78, 0x00000000); in nv50_fifo_gpfifo_new()
79 nvkm_wo32(chan->ramfc, 0x7c, 0x30000001); in nv50_fifo_gpfifo_new()
80 nvkm_wo32(chan->ramfc, 0x80, ((chan->ramht->bits - 9) << 27) | in nv50_fifo_gpfifo_new()
Dgv100.c39 nvkm_wo32(memory, offset + 0x0, lower_32_bits(user)); in gv100_fifo_runlist_chan()
40 nvkm_wo32(memory, offset + 0x4, upper_32_bits(user)); in gv100_fifo_runlist_chan()
41 nvkm_wo32(memory, offset + 0x8, lower_32_bits(inst) | chan->base.chid); in gv100_fifo_runlist_chan()
42 nvkm_wo32(memory, offset + 0xc, upper_32_bits(inst)); in gv100_fifo_runlist_chan()
49 nvkm_wo32(memory, offset + 0x0, (128 << 24) | (3 << 16) | 0x00000001); in gv100_fifo_runlist_cgrp()
50 nvkm_wo32(memory, offset + 0x4, cgrp->chan_nr); in gv100_fifo_runlist_cgrp()
51 nvkm_wo32(memory, offset + 0x8, cgrp->id); in gv100_fifo_runlist_cgrp()
52 nvkm_wo32(memory, offset + 0xc, 0x00000000); in gv100_fifo_runlist_cgrp()
Dchang84.c121 nvkm_wo32(chan->eng, offset + 0x00, 0x00000000); in g84_fifo_chan_engine_fini()
122 nvkm_wo32(chan->eng, offset + 0x04, 0x00000000); in g84_fifo_chan_engine_fini()
123 nvkm_wo32(chan->eng, offset + 0x08, 0x00000000); in g84_fifo_chan_engine_fini()
124 nvkm_wo32(chan->eng, offset + 0x0c, 0x00000000); in g84_fifo_chan_engine_fini()
125 nvkm_wo32(chan->eng, offset + 0x10, 0x00000000); in g84_fifo_chan_engine_fini()
126 nvkm_wo32(chan->eng, offset + 0x14, 0x00000000); in g84_fifo_chan_engine_fini()
148 nvkm_wo32(chan->eng, offset + 0x00, 0x00190000); in g84_fifo_chan_engine_init()
149 nvkm_wo32(chan->eng, offset + 0x04, lower_32_bits(limit)); in g84_fifo_chan_engine_init()
150 nvkm_wo32(chan->eng, offset + 0x08, lower_32_bits(start)); in g84_fifo_chan_engine_init()
151 nvkm_wo32(chan->eng, offset + 0x0c, upper_32_bits(limit) << 24 | in g84_fifo_chan_engine_init()
[all …]
Dchannv50.c89 nvkm_wo32(chan->eng, offset + 0x00, 0x00000000); in nv50_fifo_chan_engine_fini()
90 nvkm_wo32(chan->eng, offset + 0x04, 0x00000000); in nv50_fifo_chan_engine_fini()
91 nvkm_wo32(chan->eng, offset + 0x08, 0x00000000); in nv50_fifo_chan_engine_fini()
92 nvkm_wo32(chan->eng, offset + 0x0c, 0x00000000); in nv50_fifo_chan_engine_fini()
93 nvkm_wo32(chan->eng, offset + 0x10, 0x00000000); in nv50_fifo_chan_engine_fini()
94 nvkm_wo32(chan->eng, offset + 0x14, 0x00000000); in nv50_fifo_chan_engine_fini()
117 nvkm_wo32(chan->eng, offset + 0x00, 0x00190000); in nv50_fifo_chan_engine_init()
118 nvkm_wo32(chan->eng, offset + 0x04, lower_32_bits(limit)); in nv50_fifo_chan_engine_init()
119 nvkm_wo32(chan->eng, offset + 0x08, lower_32_bits(start)); in nv50_fifo_chan_engine_init()
120 nvkm_wo32(chan->eng, offset + 0x0c, upper_32_bits(limit) << 24 | in nv50_fifo_chan_engine_init()
[all …]
Ddmanv40.c80 nvkm_wo32(imem->ramfc, chan->ramfc + ctx, 0x00000000); in nv40_fifo_dma_engine_fini()
111 nvkm_wo32(imem->ramfc, chan->ramfc + ctx, inst); in nv40_fifo_dma_engine_init()
225 nvkm_wo32(imem->ramfc, chan->ramfc + 0x00, args->v0.offset); in nv40_fifo_dma_new()
226 nvkm_wo32(imem->ramfc, chan->ramfc + 0x04, args->v0.offset); in nv40_fifo_dma_new()
227 nvkm_wo32(imem->ramfc, chan->ramfc + 0x0c, chan->base.push->addr >> 4); in nv40_fifo_dma_new()
228 nvkm_wo32(imem->ramfc, chan->ramfc + 0x18, 0x30000000 | in nv40_fifo_dma_new()
235 nvkm_wo32(imem->ramfc, chan->ramfc + 0x3c, 0x0001ffff); in nv40_fifo_dma_new()
Ddmanv17.c78 nvkm_wo32(imem->ramfc, chan->ramfc + 0x00, args->v0.offset); in nv17_fifo_dma_new()
79 nvkm_wo32(imem->ramfc, chan->ramfc + 0x04, args->v0.offset); in nv17_fifo_dma_new()
80 nvkm_wo32(imem->ramfc, chan->ramfc + 0x0c, chan->base.push->addr >> 4); in nv17_fifo_dma_new()
81 nvkm_wo32(imem->ramfc, chan->ramfc + 0x14, in nv17_fifo_dma_new()
/drivers/gpu/drm/nouveau/nvkm/subdev/mmu/
Dvmmgv100.c43 nvkm_wo32(inst, 0x21c, 0x00000000); in gv100_vmm_join()
47 nvkm_wo32(inst, 0x2a4 + (i * 0x10), data[1]); in gv100_vmm_join()
48 nvkm_wo32(inst, 0x2a0 + (i * 0x10), data[0]); in gv100_vmm_join()
50 nvkm_wo32(inst, 0x2a4 + (i * 0x10), 0x00000001); in gv100_vmm_join()
51 nvkm_wo32(inst, 0x2a0 + (i * 0x10), 0x00000001); in gv100_vmm_join()
53 nvkm_wo32(inst, 0x2a8 + (i * 0x10), 0x00000000); in gv100_vmm_join()
56 nvkm_wo32(inst, 0x298, lower_32_bits(mask)); in gv100_vmm_join()
57 nvkm_wo32(inst, 0x29c, upper_32_bits(mask)); in gv100_vmm_join()
/drivers/gpu/drm/nouveau/nvkm/subdev/bar/
Dnv50.c156 nvkm_wo32(bar->bar2, 0x00, 0x7fc00000); in nv50_bar_oneinit()
157 nvkm_wo32(bar->bar2, 0x04, lower_32_bits(limit)); in nv50_bar_oneinit()
158 nvkm_wo32(bar->bar2, 0x08, lower_32_bits(start)); in nv50_bar_oneinit()
159 nvkm_wo32(bar->bar2, 0x0c, upper_32_bits(limit) << 24 | in nv50_bar_oneinit()
161 nvkm_wo32(bar->bar2, 0x10, 0x00000000); in nv50_bar_oneinit()
162 nvkm_wo32(bar->bar2, 0x14, 0x00000000); in nv50_bar_oneinit()
192 nvkm_wo32(bar->bar1, 0x00, 0x7fc00000); in nv50_bar_oneinit()
193 nvkm_wo32(bar->bar1, 0x04, lower_32_bits(limit)); in nv50_bar_oneinit()
194 nvkm_wo32(bar->bar1, 0x08, lower_32_bits(start)); in nv50_bar_oneinit()
195 nvkm_wo32(bar->bar1, 0x0c, upper_32_bits(limit) << 24 | in nv50_bar_oneinit()
[all …]
/drivers/gpu/drm/nouveau/nvkm/engine/dma/
Dusergf119.c50 nvkm_wo32(*pgpuobj, 0x00, dmaobj->flags0); in gf119_dmaobj_bind()
51 nvkm_wo32(*pgpuobj, 0x04, dmaobj->base.start >> 8); in gf119_dmaobj_bind()
52 nvkm_wo32(*pgpuobj, 0x08, dmaobj->base.limit >> 8); in gf119_dmaobj_bind()
53 nvkm_wo32(*pgpuobj, 0x0c, 0x00000000); in gf119_dmaobj_bind()
54 nvkm_wo32(*pgpuobj, 0x10, 0x00000000); in gf119_dmaobj_bind()
55 nvkm_wo32(*pgpuobj, 0x14, 0x00000000); in gf119_dmaobj_bind()
Dusergf100.c51 nvkm_wo32(*pgpuobj, 0x00, dmaobj->flags0); in gf100_dmaobj_bind()
52 nvkm_wo32(*pgpuobj, 0x04, lower_32_bits(dmaobj->base.limit)); in gf100_dmaobj_bind()
53 nvkm_wo32(*pgpuobj, 0x08, lower_32_bits(dmaobj->base.start)); in gf100_dmaobj_bind()
54 nvkm_wo32(*pgpuobj, 0x0c, upper_32_bits(dmaobj->base.limit) << 24 | in gf100_dmaobj_bind()
56 nvkm_wo32(*pgpuobj, 0x10, 0x00000000); in gf100_dmaobj_bind()
57 nvkm_wo32(*pgpuobj, 0x14, dmaobj->flags5); in gf100_dmaobj_bind()
Dusernv50.c51 nvkm_wo32(*pgpuobj, 0x00, dmaobj->flags0); in nv50_dmaobj_bind()
52 nvkm_wo32(*pgpuobj, 0x04, lower_32_bits(dmaobj->base.limit)); in nv50_dmaobj_bind()
53 nvkm_wo32(*pgpuobj, 0x08, lower_32_bits(dmaobj->base.start)); in nv50_dmaobj_bind()
54 nvkm_wo32(*pgpuobj, 0x0c, upper_32_bits(dmaobj->base.limit) << 24 | in nv50_dmaobj_bind()
56 nvkm_wo32(*pgpuobj, 0x10, 0x00000000); in nv50_dmaobj_bind()
57 nvkm_wo32(*pgpuobj, 0x14, dmaobj->flags5); in nv50_dmaobj_bind()
Dusergv100.c50 nvkm_wo32(*pgpuobj, 0x00, dmaobj->flags0); in gv100_dmaobj_bind()
51 nvkm_wo32(*pgpuobj, 0x04, lower_32_bits(start)); in gv100_dmaobj_bind()
52 nvkm_wo32(*pgpuobj, 0x08, upper_32_bits(start)); in gv100_dmaobj_bind()
53 nvkm_wo32(*pgpuobj, 0x0c, lower_32_bits(limit)); in gv100_dmaobj_bind()
54 nvkm_wo32(*pgpuobj, 0x10, upper_32_bits(limit)); in gv100_dmaobj_bind()
/drivers/gpu/drm/nouveau/nvkm/engine/cipher/
Dg84.c41 nvkm_wo32(*pgpuobj, 0x00, object->oclass); in g84_cipher_oclass_bind()
42 nvkm_wo32(*pgpuobj, 0x04, 0x00000000); in g84_cipher_oclass_bind()
43 nvkm_wo32(*pgpuobj, 0x08, 0x00000000); in g84_cipher_oclass_bind()
44 nvkm_wo32(*pgpuobj, 0x0c, 0x00000000); in g84_cipher_oclass_bind()

123