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Searched refs:pin (Results 1 – 25 of 419) sorted by relevance

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/drivers/media/cec/core/
Dcec-pin.c111 static void cec_pin_update(struct cec_pin *pin, bool v, bool force) in cec_pin_update() argument
113 if (!force && v == pin->adap->cec_pin_is_high) in cec_pin_update()
116 pin->adap->cec_pin_is_high = v; in cec_pin_update()
117 if (atomic_read(&pin->work_pin_num_events) < CEC_NUM_PIN_EVENTS) { in cec_pin_update()
120 if (pin->work_pin_events_dropped) { in cec_pin_update()
121 pin->work_pin_events_dropped = false; in cec_pin_update()
124 pin->work_pin_events[pin->work_pin_events_wr] = ev; in cec_pin_update()
125 pin->work_pin_ts[pin->work_pin_events_wr] = ktime_get(); in cec_pin_update()
126 pin->work_pin_events_wr = in cec_pin_update()
127 (pin->work_pin_events_wr + 1) % CEC_NUM_PIN_EVENTS; in cec_pin_update()
[all …]
Dcec-pin-error-inj.c49 u16 cec_pin_rx_error_inj(struct cec_pin *pin) in cec_pin_rx_error_inj() argument
54 if (!(pin->error_inj[cmd] & CEC_ERROR_INJ_RX_MASK) && in cec_pin_rx_error_inj()
55 pin->rx_bit >= 18) in cec_pin_rx_error_inj()
56 cmd = pin->rx_msg.msg[1]; in cec_pin_rx_error_inj()
57 return (pin->error_inj[cmd] & CEC_ERROR_INJ_RX_MASK) ? cmd : in cec_pin_rx_error_inj()
61 u16 cec_pin_tx_error_inj(struct cec_pin *pin) in cec_pin_tx_error_inj() argument
65 if (!(pin->error_inj[cmd] & CEC_ERROR_INJ_TX_MASK) && in cec_pin_tx_error_inj()
66 pin->tx_msg.len > 1) in cec_pin_tx_error_inj()
67 cmd = pin->tx_msg.msg[1]; in cec_pin_tx_error_inj()
68 return (pin->error_inj[cmd] & CEC_ERROR_INJ_TX_MASK) ? cmd : in cec_pin_tx_error_inj()
[all …]
/drivers/pinctrl/renesas/
Dpinctrl-rza1.c82 u8 pin: 4; member
99 u16 pin: 4; member
126 { .pin = 0, .func = 1 },
127 { .pin = 1, .func = 1 },
128 { .pin = 2, .func = 1 },
129 { .pin = 3, .func = 1 },
130 { .pin = 4, .func = 1 },
131 { .pin = 5, .func = 1 },
132 { .pin = 6, .func = 1 },
133 { .pin = 7, .func = 1 },
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DKconfig9 bool "Renesas SoC pin control support" if COMPILE_TEST && !(ARCH_RENESAS || SUPERH)
53 This enables pin control drivers for Renesas SuperH and ARM platforms
61 This enables common pin control functionality for EMMA Mobile, R-Car,
69 This enables pin control and GPIO drivers for SH/SH Mobile platforms
78 bool "pin control support for Emma Mobile EV2" if COMPILE_TEST
82 bool "pin control support for R-Car D3" if COMPILE_TEST
86 bool "pin control support for R-Car E2" if COMPILE_TEST
90 bool "pin control support for R-Car E3" if COMPILE_TEST
94 bool "pin control support for R-Car H1" if COMPILE_TEST
98 bool "pin control support for R-Car H2" if COMPILE_TEST
[all …]
/drivers/pinctrl/qcom/
Dpinctrl-ssbi-mpp.c165 struct pm8xxx_pin_data *pin) in pm8xxx_mpp_update() argument
173 switch (pin->mode) { in pm8xxx_mpp_update()
175 if (pin->dtest) { in pm8xxx_mpp_update()
177 ctrl = pin->dtest - 1; in pm8xxx_mpp_update()
178 } else if (pin->input && pin->output) { in pm8xxx_mpp_update()
180 if (pin->high_z) in pm8xxx_mpp_update()
182 else if (pin->pullup == 600) in pm8xxx_mpp_update()
184 else if (pin->pullup == 10000) in pm8xxx_mpp_update()
188 } else if (pin->input) { in pm8xxx_mpp_update()
190 if (pin->dtest) in pm8xxx_mpp_update()
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Dpinctrl-ssbi-gpio.c126 struct pm8xxx_pin_data *pin, int bank) in pm8xxx_read_bank() argument
131 ret = regmap_write(pctrl->regmap, pin->reg, val); in pm8xxx_read_bank()
137 ret = regmap_read(pctrl->regmap, pin->reg, &val); in pm8xxx_read_bank()
147 struct pm8xxx_pin_data *pin, in pm8xxx_write_bank() argument
156 ret = regmap_write(pctrl->regmap, pin->reg, val); in pm8xxx_write_bank()
226 struct pm8xxx_pin_data *pin = pctrl->desc.pins[group].drv_data; in pm8xxx_pinmux_set_mux() local
229 pin->function = function; in pm8xxx_pinmux_set_mux()
230 val = pin->function << 1; in pm8xxx_pinmux_set_mux()
232 pm8xxx_write_bank(pctrl, pin, 4, val); in pm8xxx_pinmux_set_mux()
249 struct pm8xxx_pin_data *pin = pctrl->desc.pins[offset].drv_data; in pm8xxx_pin_config_get() local
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/drivers/pinctrl/aspeed/
Dpinmux-aspeed.h595 #define SIG_EXPR_LIST_ALIAS(pin, sig, group) \ argument
597 SIG_EXPR_LIST_SYM(pin, sig)[ARRAY_SIZE(SIG_EXPR_LIST_SYM(sig, group))] \
613 #define SIG_EXPR_LIST_DECL_SESG(pin, sig, func, ...) \ argument
617 SIG_EXPR_LIST_ALIAS(pin, sig, func)
629 #define SIG_EXPR_LIST_DECL_SEMG(pin, sig, group, func, ...) \ argument
633 SIG_EXPR_LIST_ALIAS(pin, sig, group)
645 #define SIG_EXPR_LIST_DECL_DESG(pin, sig, f0, f1) \ argument
649 SIG_EXPR_LIST_ALIAS(pin, sig, f0)
653 #define PIN_EXPRS_SYM(pin) pin_exprs_ ## pin argument
654 #define PIN_EXPRS_PTR(pin) (&PIN_EXPRS_SYM(pin)[0]) argument
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/drivers/pinctrl/mediatek/
Dpinctrl-mtk-common.c54 unsigned long pin) in mtk_get_regmap() argument
56 if (pin >= pctl->devdata->type1_start && pin < pctl->devdata->type1_end) in mtk_get_regmap()
61 static unsigned int mtk_get_port(struct mtk_pinctrl *pctl, unsigned long pin) in mtk_get_port() argument
64 return ((pin >> 4) & pctl->devdata->port_mask) in mtk_get_port()
109 static int mtk_pconf_set_ies_smt(struct mtk_pinctrl *pctl, unsigned pin, in mtk_pconf_set_ies_smt() argument
134 return pctl->devdata->spec_ies_smt_set(mtk_get_regmap(pctl, pin), in mtk_pconf_set_ies_smt()
135 pin, pctl->devdata->port_align, value, arg); in mtk_pconf_set_ies_smt()
138 bit = BIT(pin & 0xf); in mtk_pconf_set_ies_smt()
146 reg_addr = SET_ADDR(mtk_get_port(pctl, pin) + offset, pctl); in mtk_pconf_set_ies_smt()
148 reg_addr = CLR_ADDR(mtk_get_port(pctl, pin) + offset, pctl); in mtk_pconf_set_ies_smt()
[all …]
/drivers/gpio/
Dgpio-vr41xx.c114 unsigned int pin; in mask_ack_giuint_low() local
116 pin = GPIO_PIN_OF_IRQ(d->irq); in mask_ack_giuint_low()
117 giu_clear(GIUINTENL, 1 << pin); in mask_ack_giuint_low()
118 giu_write(GIUINTSTATL, 1 << pin); in mask_ack_giuint_low()
172 unsigned int pin; in mask_ack_giuint_high() local
174 pin = GPIO_PIN_OF_IRQ(d->irq) - GIUINT_HIGH_OFFSET; in mask_ack_giuint_high()
175 giu_clear(GIUINTENH, 1 << pin); in mask_ack_giuint_high()
176 giu_write(GIUINTSTATH, 1 << pin); in mask_ack_giuint_high()
223 void vr41xx_set_irq_trigger(unsigned int pin, irq_trigger_t trigger, in vr41xx_set_irq_trigger() argument
228 if (pin < GIUINT_HIGH_OFFSET) { in vr41xx_set_irq_trigger()
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Dgpio-lpc32xx.c179 unsigned pin, int input) in __set_gpio_dir_p012() argument
182 gpreg_write(group, GPIO012_PIN_TO_BIT(pin), in __set_gpio_dir_p012()
185 gpreg_write(group, GPIO012_PIN_TO_BIT(pin), in __set_gpio_dir_p012()
190 unsigned pin, int input) in __set_gpio_dir_p3() argument
192 u32 u = GPIO3_PIN_TO_BIT(pin); in __set_gpio_dir_p3()
201 unsigned pin, int high) in __set_gpio_level_p012() argument
204 gpreg_write(group, GPIO012_PIN_TO_BIT(pin), in __set_gpio_level_p012()
207 gpreg_write(group, GPIO012_PIN_TO_BIT(pin), in __set_gpio_level_p012()
212 unsigned pin, int high) in __set_gpio_level_p3() argument
214 u32 u = GPIO3_PIN_TO_BIT(pin); in __set_gpio_level_p3()
[all …]
Dgpio-zevio.c60 static inline u32 zevio_gpio_port_get(struct zevio_gpio *c, unsigned pin, in zevio_gpio_port_get() argument
63 unsigned section_offset = ((pin >> 3) & 3)*ZEVIO_GPIO_SECTION_SIZE; in zevio_gpio_port_get()
67 static inline void zevio_gpio_port_set(struct zevio_gpio *c, unsigned pin, in zevio_gpio_port_set() argument
70 unsigned section_offset = ((pin >> 3) & 3)*ZEVIO_GPIO_SECTION_SIZE; in zevio_gpio_port_set()
75 static int zevio_gpio_get(struct gpio_chip *chip, unsigned pin) in zevio_gpio_get() argument
81 dir = zevio_gpio_port_get(controller, pin, ZEVIO_GPIO_DIRECTION); in zevio_gpio_get()
82 if (dir & BIT(ZEVIO_GPIO_BIT(pin))) in zevio_gpio_get()
83 val = zevio_gpio_port_get(controller, pin, ZEVIO_GPIO_INPUT); in zevio_gpio_get()
85 val = zevio_gpio_port_get(controller, pin, ZEVIO_GPIO_OUTPUT); in zevio_gpio_get()
88 return (val >> ZEVIO_GPIO_BIT(pin)) & 0x1; in zevio_gpio_get()
[all …]
Dgpio-dln2.c66 __le16 pin; member
70 __le16 pin __packed;
89 static int dln2_gpio_pin_cmd(struct dln2_gpio *dln2, int cmd, unsigned pin) in dln2_gpio_pin_cmd() argument
92 .pin = cpu_to_le16(pin), in dln2_gpio_pin_cmd()
98 static int dln2_gpio_pin_val(struct dln2_gpio *dln2, int cmd, unsigned int pin) in dln2_gpio_pin_val() argument
102 .pin = cpu_to_le16(pin), in dln2_gpio_pin_val()
110 if (len < sizeof(rsp) || req.pin != rsp.pin) in dln2_gpio_pin_val()
116 static int dln2_gpio_pin_get_in_val(struct dln2_gpio *dln2, unsigned int pin) in dln2_gpio_pin_get_in_val() argument
120 ret = dln2_gpio_pin_val(dln2, DLN2_GPIO_PIN_GET_VAL, pin); in dln2_gpio_pin_get_in_val()
126 static int dln2_gpio_pin_get_out_val(struct dln2_gpio *dln2, unsigned int pin) in dln2_gpio_pin_get_out_val() argument
[all …]
Dgpio-sama5d2-piobu.c58 static int sama5d2_piobu_setup_pin(struct gpio_chip *chip, unsigned int pin) in sama5d2_piobu_setup_pin() argument
63 unsigned int mask = BIT(PIOBU_DET_OFFSET + pin); in sama5d2_piobu_setup_pin()
79 static int sama5d2_piobu_write_value(struct gpio_chip *chip, unsigned int pin, in sama5d2_piobu_write_value() argument
86 reg = PIOBU_BASE + pin * PIOBU_REG_SIZE; in sama5d2_piobu_write_value()
95 static int sama5d2_piobu_read_value(struct gpio_chip *chip, unsigned int pin, in sama5d2_piobu_read_value() argument
103 reg = PIOBU_BASE + pin * PIOBU_REG_SIZE; in sama5d2_piobu_read_value()
115 unsigned int pin) in sama5d2_piobu_get_direction() argument
117 int ret = sama5d2_piobu_read_value(chip, pin, PIOBU_DIRECTION); in sama5d2_piobu_get_direction()
130 unsigned int pin) in sama5d2_piobu_direction_input() argument
132 return sama5d2_piobu_write_value(chip, pin, PIOBU_DIRECTION, PIOBU_IN); in sama5d2_piobu_direction_input()
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/drivers/acpi/
Dpci_irq.c32 u8 pin; member
37 static inline char pin_name(int pin) in pin_name() argument
39 return 'A' + pin - 1; in pin_name()
88 unsigned char pin; member
126 entry->pin == quirk->pin && in do_prt_fixups()
133 entry->id.device, pin_name(entry->pin), in do_prt_fixups()
141 int pin, struct acpi_pci_routing_table *prt, in acpi_pci_irq_check_entry() argument
150 prt->pin + 1 != pin) in acpi_pci_irq_check_entry()
165 entry->pin = prt->pin + 1; in acpi_pci_irq_check_entry()
198 entry->id.device, pin_name(entry->pin), in acpi_pci_irq_check_entry()
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/drivers/gpu/drm/i915/display/
Dintel_hotplug.c140 enum hpd_pin pin, bool long_hpd) in intel_hpd_irq_storm_detect() argument
143 unsigned long start = hpd->stats[pin].last_jiffies; in intel_hpd_irq_storm_detect()
154 hpd->stats[pin].last_jiffies = jiffies; in intel_hpd_irq_storm_detect()
155 hpd->stats[pin].count = 0; in intel_hpd_irq_storm_detect()
158 hpd->stats[pin].count += increment; in intel_hpd_irq_storm_detect()
159 if (hpd->stats[pin].count > threshold) { in intel_hpd_irq_storm_detect()
160 hpd->stats[pin].state = HPD_MARK_DISABLED; in intel_hpd_irq_storm_detect()
162 "HPD interrupt storm detected on PIN %d\n", pin); in intel_hpd_irq_storm_detect()
167 pin, in intel_hpd_irq_storm_detect()
168 hpd->stats[pin].count); in intel_hpd_irq_storm_detect()
[all …]
/drivers/pinctrl/
Dpinctrl-at91.c123 uint32_t pin; member
176 bool (*get_deglitch)(void __iomem *pio, unsigned pin);
178 bool (*get_debounce)(void __iomem *pio, unsigned pin, u32 *div);
180 bool (*get_pulldown)(void __iomem *pio, unsigned pin);
182 bool (*get_schmitt_trig)(void __iomem *pio, unsigned pin);
184 unsigned (*get_drivestrength)(void __iomem *pio, unsigned pin);
185 void (*set_drivestrength)(void __iomem *pio, unsigned pin,
187 unsigned (*get_slewrate)(void __iomem *pio, unsigned pin);
188 void (*set_slewrate)(void __iomem *pio, unsigned pin, u32 slewrate);
350 static inline int pin_to_bank(unsigned pin) in pin_to_bank() argument
[all …]
Dpinctrl-max77620.c270 unsigned int pin, unsigned long *config) in max77620_pinconf_get() argument
281 if (mpci->pin_info[pin].drv_type == MAX77620_PIN_OD_DRV) in max77620_pinconf_get()
286 if (mpci->pin_info[pin].drv_type == MAX77620_PIN_PP_DRV) in max77620_pinconf_get()
296 if (val & BIT(pin)) in max77620_pinconf_get()
306 if (val & BIT(pin)) in max77620_pinconf_get()
337 int pin, int param) in max77620_set_fps_param() argument
339 struct max77620_fps_config *fps_config = &mpci->fps_config[pin]; in max77620_set_fps_param()
344 if ((pin < MAX77620_GPIO1) || (pin > MAX77620_GPIO3)) in max77620_set_fps_param()
347 addr = MAX77620_REG_FPS_GPIO1 + pin - 1; in max77620_set_fps_param()
378 param, pin); in max77620_set_fps_param()
[all …]
Dpinctrl-pistachio.c26 #define PADS_SCHMITT_EN_REG(pin) (PADS_SCHMITT_EN0 + 0x4 * ((pin) / 32)) argument
27 #define PADS_SCHMITT_EN_BIT(pin) BIT((pin) % 32) argument
30 #define PADS_PU_PD_REG(pin) (PADS_PU_PD0 + 0x4 * ((pin) / 16)) argument
31 #define PADS_PU_PD_SHIFT(pin) (2 * ((pin) % 16)) argument
44 #define PADS_SLEW_RATE_REG(pin) (PADS_SLEW_RATE0 + 0x4 * ((pin) / 32)) argument
45 #define PADS_SLEW_RATE_BIT(pin) BIT((pin) % 32) argument
48 #define PADS_DRIVE_STRENGTH_REG(pin) \ argument
49 (PADS_DRIVE_STRENGTH0 + 0x4 * ((pin) / 16))
50 #define PADS_DRIVE_STRENGTH_SHIFT(pin) (2 * ((pin) % 16)) argument
86 unsigned int pin; member
[all …]
/drivers/pinctrl/sunxi/
Dpinctrl-sunxi.h32 #define SUNXI_PINCTRL_PIN(bank, pin) \ argument
33 PINCTRL_PIN(P ## bank ## _BASE + (pin), "P" #bank #pin)
125 struct pinctrl_pin_desc pin; member
149 unsigned pin; member
177 .pin = _pin, \
184 .pin = _pin, \
235 static inline u32 sunxi_mux_reg(u16 pin) in sunxi_mux_reg() argument
237 u8 bank = pin / PINS_PER_BANK; in sunxi_mux_reg()
240 offset += pin % PINS_PER_BANK / MUX_PINS_PER_REG * 0x04; in sunxi_mux_reg()
244 static inline u32 sunxi_mux_offset(u16 pin) in sunxi_mux_offset() argument
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/drivers/gpu/drm/amd/display/dc/gpio/
Dhw_gpio.c64 struct hw_gpio *pin = FROM_HW_GPIO_PIN(ptr); in dal_hw_gpio_open() local
66 store_registers(pin); in dal_hw_gpio_open()
68 ptr->opened = (dal_hw_gpio_config_mode(pin, mode) == GPIO_RESULT_OK); in dal_hw_gpio_open()
125 struct hw_gpio *pin = FROM_HW_GPIO_PIN(ptr); in dal_hw_gpio_change_mode() local
127 return dal_hw_gpio_config_mode(pin, mode); in dal_hw_gpio_change_mode()
133 struct hw_gpio *pin = FROM_HW_GPIO_PIN(ptr); in dal_hw_gpio_close() local
135 restore_registers(pin); in dal_hw_gpio_close()
180 struct hw_gpio *pin, in dal_hw_gpio_construct() argument
185 pin->base.ctx = ctx; in dal_hw_gpio_construct()
186 pin->base.id = id; in dal_hw_gpio_construct()
[all …]
/drivers/pinctrl/meson/
Dpinctrl-meson.c72 static int meson_get_bank(struct meson_pinctrl *pc, unsigned int pin, in meson_get_bank() argument
78 if (pin >= pc->data->banks[i].first && in meson_get_bank()
79 pin <= pc->data->banks[i].last) { in meson_get_bank()
97 static void meson_calc_reg_and_bit(struct meson_bank *bank, unsigned int pin, in meson_calc_reg_and_bit() argument
103 *bit = (desc->bit + pin - bank->first) * meson_bit_strides[reg_type]; in meson_calc_reg_and_bit()
180 unsigned int pin, in meson_pinconf_set_gpio_bit() argument
188 ret = meson_get_bank(pc, pin, &bank); in meson_pinconf_set_gpio_bit()
192 meson_calc_reg_and_bit(bank, pin, reg_type, &reg, &bit); in meson_pinconf_set_gpio_bit()
198 unsigned int pin, in meson_pinconf_get_gpio_bit() argument
205 ret = meson_get_bank(pc, pin, &bank); in meson_pinconf_get_gpio_bit()
[all …]
/drivers/gpu/drm/radeon/
Ddce6_afmt.c67 offset = rdev->audio.pin[i].offset; in dce6_afmt_get_connected_pins()
71 rdev->audio.pin[i].connected = false; in dce6_afmt_get_connected_pins()
73 rdev->audio.pin[i].connected = true; in dce6_afmt_get_connected_pins()
82 struct r600_audio_pin *pin = NULL; in dce6_audio_get_pin() local
88 if (rdev->audio.pin[i].connected) { in dce6_audio_get_pin()
89 pin = &rdev->audio.pin[i]; in dce6_audio_get_pin()
96 if (dig->pin == pin) in dce6_audio_get_pin()
102 return pin; in dce6_audio_get_pin()
105 if (!pin) in dce6_audio_get_pin()
107 return pin; in dce6_audio_get_pin()
[all …]
/drivers/pinctrl/pxa/
Dpinctrl-pxa2xx.c48 *pins = (unsigned *)&group->pin; in pxa2xx_pctrl_get_group_pins()
72 const struct pxa_desc_pin *pin = pctl->ppins + i; in pxa_desc_by_func_group() local
74 if (!strcmp(pin->pin.name, pin_name)) in pxa_desc_by_func_group()
75 for (df = pin->functions; df->name; df++) in pxa_desc_by_func_group()
85 unsigned pin, in pxa2xx_pmx_gpio_set_direction() argument
93 gpdr = pctl->base_gpdr[pin / 32]; in pxa2xx_pmx_gpio_set_direction()
95 pin, !input); in pxa2xx_pmx_gpio_set_direction()
100 val = (val & ~BIT(pin % 32)) | (input ? 0 : BIT(pin % 32)); in pxa2xx_pmx_gpio_set_direction()
144 int pin, shift; in pxa2xx_pmx_set_mux() local
155 pin = group->pin; in pxa2xx_pmx_set_mux()
[all …]
/drivers/pinctrl/sprd/
Dpinctrl-sprd.c177 struct sprd_pin *pin = NULL; in sprd_pinctrl_get_pin_by_id() local
182 pin = &info->pins[i]; in sprd_pinctrl_get_pin_by_id()
187 return pin; in sprd_pinctrl_get_pin_by_id()
417 struct sprd_pin *pin = sprd_pinctrl_get_pin_by_id(pctl, pin_id); in sprd_pmx_set_mux() local
419 if (!pin || pin->type != COMMON_PIN) in sprd_pmx_set_mux()
422 reg = readl((void __iomem *)pin->reg); in sprd_pmx_set_mux()
425 writel(reg, (void __iomem *)pin->reg); in sprd_pmx_set_mux()
442 struct sprd_pin *pin = sprd_pinctrl_get_pin_by_id(pctl, pin_id); in sprd_pinconf_get() local
446 if (!pin) in sprd_pinconf_get()
449 if (pin->type == GLOBAL_CTRL_PIN) { in sprd_pinconf_get()
[all …]
/drivers/pinctrl/intel/
Dpinctrl-intel.c92 unsigned int pin) in intel_get_community() argument
99 if (pin >= community->pin_base && in intel_get_community()
100 pin < community->pin_base + community->npins) in intel_get_community()
104 dev_warn(pctrl->dev, "failed to find community for pin %u\n", pin); in intel_get_community()
110 unsigned int pin) in intel_community_get_padgroup() argument
117 if (pin >= padgrp->base && pin < padgrp->base + padgrp->size) in intel_community_get_padgroup()
125 unsigned int pin, unsigned int reg) in intel_get_padcfg() argument
131 community = intel_get_community(pctrl, pin); in intel_get_padcfg()
135 padno = pin_to_padno(community, pin); in intel_get_padcfg()
144 static bool intel_pad_owned_by_host(struct intel_pinctrl *pctrl, unsigned int pin) in intel_pad_owned_by_host() argument
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