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Searched refs:pipeline (Results 1 – 25 of 64) sorted by relevance

123

/drivers/staging/media/atomisp/pci/runtime/pipeline/src/
Dpipeline.c44 struct ia_css_pipeline *pipeline,
53 static void ia_css_pipeline_set_zoom_stage(struct ia_css_pipeline *pipeline);
66 struct ia_css_pipeline *pipeline, in ia_css_pipeline_create() argument
71 assert(pipeline); in ia_css_pipeline_create()
73 pipeline, pipe_id, pipe_num, dvs_frame_delay); in ia_css_pipeline_create()
74 if (!pipeline) { in ia_css_pipeline_create()
79 pipeline_init_defaults(pipeline, pipe_id, pipe_num, dvs_frame_delay); in ia_css_pipeline_create()
108 void ia_css_pipeline_destroy(struct ia_css_pipeline *pipeline) in ia_css_pipeline_destroy() argument
110 assert(pipeline); in ia_css_pipeline_destroy()
111 IA_CSS_ENTER_PRIVATE("pipeline = %p", pipeline); in ia_css_pipeline_destroy()
[all …]
/drivers/gpu/drm/xen/
Dxen_drm_front_kms.c91 static void send_pending_event(struct xen_drm_front_drm_pipeline *pipeline) in send_pending_event() argument
93 struct drm_crtc *crtc = &pipeline->pipe.crtc; in send_pending_event()
98 if (pipeline->pending_event) in send_pending_event()
99 drm_crtc_send_vblank_event(crtc, pipeline->pending_event); in send_pending_event()
100 pipeline->pending_event = NULL; in send_pending_event()
108 struct xen_drm_front_drm_pipeline *pipeline = in display_enable() local
117 ret = xen_drm_front_mode_set(pipeline, crtc->x, crtc->y, in display_enable()
124 pipeline->conn_connected = false; in display_enable()
132 struct xen_drm_front_drm_pipeline *pipeline = in display_disable() local
137 ret = xen_drm_front_mode_set(pipeline, 0, 0, 0, 0, 0, in display_disable()
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Dxen_drm_front_conn.c49 struct xen_drm_front_drm_pipeline *pipeline = in connector_detect() local
53 pipeline->conn_connected = false; in connector_detect()
55 return pipeline->conn_connected ? connector_status_connected : in connector_detect()
63 struct xen_drm_front_drm_pipeline *pipeline = in connector_get_modes() local
74 videomode.hactive = pipeline->width; in connector_get_modes()
75 videomode.vactive = pipeline->height; in connector_get_modes()
104 struct xen_drm_front_drm_pipeline *pipeline = in xen_drm_front_conn_init() local
109 pipeline->conn_connected = true; in xen_drm_front_conn_init()
Dxen_drm_front.h129 struct xen_drm_front_drm_pipeline pipeline[XEN_DRM_FRONT_MAX_CRTCS]; member
142 int xen_drm_front_mode_set(struct xen_drm_front_drm_pipeline *pipeline,
Dxen_drm_front_kms.h23 void xen_drm_front_kms_on_frame_done(struct xen_drm_front_drm_pipeline *pipeline,
/drivers/isdn/mISDN/
Ddsp_pipeline.c159 int dsp_pipeline_init(struct dsp_pipeline *pipeline) in dsp_pipeline_init() argument
161 if (!pipeline) in dsp_pipeline_init()
164 INIT_LIST_HEAD(&pipeline->list); in dsp_pipeline_init()
169 static inline void _dsp_pipeline_destroy(struct dsp_pipeline *pipeline) in _dsp_pipeline_destroy() argument
173 list_for_each_entry_safe(entry, n, &pipeline->list, list) { in _dsp_pipeline_destroy()
176 dsp_hwec_disable(container_of(pipeline, struct dsp, in _dsp_pipeline_destroy()
177 pipeline)); in _dsp_pipeline_destroy()
184 void dsp_pipeline_destroy(struct dsp_pipeline *pipeline) in dsp_pipeline_destroy() argument
187 if (!pipeline) in dsp_pipeline_destroy()
190 _dsp_pipeline_destroy(pipeline); in dsp_pipeline_destroy()
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Ddsp.h236 pipeline; member
271 extern int dsp_pipeline_init(struct dsp_pipeline *pipeline);
272 extern void dsp_pipeline_destroy(struct dsp_pipeline *pipeline);
273 extern int dsp_pipeline_build(struct dsp_pipeline *pipeline, const char *cfg);
274 extern void dsp_pipeline_process_tx(struct dsp_pipeline *pipeline, u8 *data,
276 extern void dsp_pipeline_process_rx(struct dsp_pipeline *pipeline, u8 *data,
/drivers/staging/media/atomisp/pci/runtime/pipeline/interface/
Dia_css_pipeline.h104 struct ia_css_pipeline *pipeline,
115 void ia_css_pipeline_destroy(struct ia_css_pipeline *pipeline);
125 struct ia_css_pipeline *pipeline);
133 int ia_css_pipeline_request_stop(struct ia_css_pipeline *pipeline);
149 void ia_css_pipeline_clean(struct ia_css_pipeline *pipeline);
163 struct ia_css_pipeline *pipeline,
174 void ia_css_pipeline_finalize_stages(struct ia_css_pipeline *pipeline,
183 int ia_css_pipeline_get_stage(struct ia_css_pipeline *pipeline,
197 *pipeline,
211 *pipeline,
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/drivers/gpu/drm/msm/disp/mdp5/
Dmdp5_crtc.c91 struct mdp5_pipeline *pipeline = &mdp5_cstate->pipeline; in crtc_flush() local
98 return mdp5_ctl_commit(ctl, pipeline, flush_mask, start); in crtc_flush()
123 mixer = mdp5_cstate->pipeline.mixer; in crtc_flush_all()
126 r_mixer = mdp5_cstate->pipeline.r_mixer; in crtc_flush_all()
137 struct mdp5_pipeline *pipeline = &mdp5_cstate->pipeline; in complete_flip() local
155 mdp5_ctl_blend(ctl, pipeline, NULL, NULL, 0, 0); in complete_flip()
214 struct mdp5_pipeline *pipeline = &mdp5_cstate->pipeline; in blend_setup() local
219 struct mdp5_hw_mixer *mixer = pipeline->mixer; in blend_setup()
221 struct mdp5_hw_mixer *r_mixer = pipeline->r_mixer; in blend_setup()
353 mdp5_ctl_blend(ctl, pipeline, stage, r_stage, plane_cnt, in blend_setup()
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Dmdp5_ctl.c135 static void set_ctl_op(struct mdp5_ctl *ctl, struct mdp5_pipeline *pipeline) in set_ctl_op() argument
138 struct mdp5_interface *intf = pipeline->intf; in set_ctl_op()
159 if (pipeline->r_mixer) in set_ctl_op()
168 int mdp5_ctl_set_pipeline(struct mdp5_ctl *ctl, struct mdp5_pipeline *pipeline) in mdp5_ctl_set_pipeline() argument
171 struct mdp5_interface *intf = pipeline->intf; in mdp5_ctl_set_pipeline()
177 set_ctl_op(ctl, pipeline); in mdp5_ctl_set_pipeline()
183 struct mdp5_pipeline *pipeline) in start_signal_needed() argument
185 struct mdp5_interface *intf = pipeline->intf; in start_signal_needed()
225 struct mdp5_pipeline *pipeline, in mdp5_ctl_set_encoder_state() argument
228 struct mdp5_interface *intf = pipeline->intf; in mdp5_ctl_set_encoder_state()
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Dmdp5_cmd_encoder.c126 struct mdp5_pipeline *pipeline = mdp5_crtc_get_pipeline(encoder->crtc); in mdp5_cmd_encoder_disable() local
133 mdp5_ctl_set_encoder_state(ctl, pipeline, false); in mdp5_cmd_encoder_disable()
134 mdp5_ctl_commit(ctl, pipeline, mdp_ctl_flush_mask_encoder(intf), true); in mdp5_cmd_encoder_disable()
144 struct mdp5_pipeline *pipeline = mdp5_crtc_get_pipeline(encoder->crtc); in mdp5_cmd_encoder_enable() local
152 mdp5_ctl_commit(ctl, pipeline, mdp_ctl_flush_mask_encoder(intf), true); in mdp5_cmd_encoder_enable()
154 mdp5_ctl_set_encoder_state(ctl, pipeline, true); in mdp5_cmd_encoder_enable()
Dmdp5_ctl.h37 int mdp5_ctl_set_cursor(struct mdp5_ctl *ctl, struct mdp5_pipeline *pipeline,
55 int mdp5_ctl_blend(struct mdp5_ctl *ctl, struct mdp5_pipeline *pipeline,
72 u32 mdp5_ctl_commit(struct mdp5_ctl *ctl, struct mdp5_pipeline *pipeline,
Dmdp5_encoder.c136 struct mdp5_pipeline *pipeline = mdp5_crtc_get_pipeline(encoder->crtc); in mdp5_vid_encoder_disable() local
145 mdp5_ctl_set_encoder_state(ctl, pipeline, false); in mdp5_vid_encoder_disable()
150 mdp5_ctl_commit(ctl, pipeline, mdp_ctl_flush_mask_encoder(intf), true); in mdp5_vid_encoder_disable()
171 struct mdp5_pipeline *pipeline = mdp5_crtc_get_pipeline(encoder->crtc); in mdp5_vid_encoder_enable() local
181 mdp5_ctl_commit(ctl, pipeline, mdp_ctl_flush_mask_encoder(intf), true); in mdp5_vid_encoder_enable()
183 mdp5_ctl_set_encoder_state(ctl, pipeline, true); in mdp5_vid_encoder_enable()
237 mdp5_cstate->pipeline.intf = intf; in mdp5_encoder_atomic_check()
/drivers/net/wireless/ti/wl18xx/
Ddebugfs.c143 WL18XX_DEBUGFS_FWSTATS_FILE(pipeline, hs_tx_stat_fifo_int, "%u");
144 WL18XX_DEBUGFS_FWSTATS_FILE(pipeline, enc_tx_stat_fifo_int, "%u");
145 WL18XX_DEBUGFS_FWSTATS_FILE(pipeline, enc_rx_stat_fifo_int, "%u");
146 WL18XX_DEBUGFS_FWSTATS_FILE(pipeline, rx_complete_stat_fifo_int, "%u");
147 WL18XX_DEBUGFS_FWSTATS_FILE(pipeline, pre_proc_swi, "%u");
148 WL18XX_DEBUGFS_FWSTATS_FILE(pipeline, post_proc_swi, "%u");
149 WL18XX_DEBUGFS_FWSTATS_FILE(pipeline, sec_frag_swi, "%u");
150 WL18XX_DEBUGFS_FWSTATS_FILE(pipeline, pre_to_defrag_swi, "%u");
151 WL18XX_DEBUGFS_FWSTATS_FILE(pipeline, defrag_to_rx_xfer_swi, "%u");
152 WL18XX_DEBUGFS_FWSTATS_FILE(pipeline, dec_packet_in, "%u");
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/drivers/staging/media/atomisp/pci/runtime/binary/src/
Dbinary.c82 + info->pipeline.left_cropping + binary_dvs_env.width; in ia_css_binary_internal_res()
84 + info->pipeline.top_cropping + binary_dvs_env.height; in ia_css_binary_internal_res()
103 info->pipeline.left_cropping, info->pipeline.mode, in ia_css_binary_internal_res()
104 info->pipeline.c_subsampling, in ia_css_binary_internal_res()
105 info->output.num_chunks, info->pipeline.pipelining); in ia_css_binary_internal_res()
107 info->pipeline.top_cropping, in ia_css_binary_internal_res()
214 if (need_bds_factor_2_00 && binary->info->sp.pipeline.left_cropping > 0) in ia_css_binary_compute_shading_table_bayer_origin()
363 if (binary->info->sp.pipeline.left_cropping > 0 && in sh_css_binary_get_sc_requirements()
372 - _ISP_BQS(binary->info->sp.pipeline.left_cropping); in sh_css_binary_get_sc_requirements()
382 binary->info->sp.pipeline.left_cropping, in sh_css_binary_get_sc_requirements()
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/drivers/staging/media/atomisp/pci/
Datomisp_acc.c123 if (asd->acc.pipeline) in atomisp_acc_release()
167 if (asd->acc.pipeline || asd->acc.extension_mode) in atomisp_acc_load_to_pipe()
230 if (asd->acc.pipeline || asd->acc.extension_mode) in atomisp_acc_unload()
251 if (asd->acc.pipeline || asd->acc.extension_mode) in atomisp_acc_start()
309 if (!asd->acc.pipeline) in atomisp_acc_wait()
344 if (asd->acc.pipeline) in atomisp_acc_map()
399 if (asd->acc.pipeline) in atomisp_acc_unmap()
420 if (asd->acc.pipeline) in atomisp_acc_s_mapped_arg()
467 if (asd->acc.pipeline || asd->acc.extension_mode) in atomisp_acc_load_extensions()
Dsh_css_param_shading.c258 left_cropping = (binary->info->sp.pipeline.left_cropping == 0) ? in prepare_shading_table()
264 left_padding = (left_padding + binary->info->sp.pipeline.left_cropping) * in prepare_shading_table()
266 binary->info->sp.pipeline.left_cropping; in prepare_shading_table()
270 top_padding = binary->info->sp.pipeline.top_cropping * bds_numerator / in prepare_shading_table()
272 binary->info->sp.pipeline.top_cropping; in prepare_shading_table()
Dsh_css.c310 sh_css_pipeline_add_acc_stage(struct ia_css_pipeline *pipeline,
547 if (pipe->pipeline.stages) in sh_css_config_input_network()
548 binary = pipe->pipeline.stages->binary; in sh_css_config_input_network()
1092 if (pipe->pipeline.stages) in sh_css_config_input_network()
1093 if (pipe->pipeline.stages->binary) in sh_css_config_input_network()
1094 binary = pipe->pipeline.stages->binary; in sh_css_config_input_network()
1373 if (binary && binary->info->sp.pipeline.mode == IA_CSS_BINARY_MODE_VIDEO) in start_binary()
1454 sh_css_sp_init_pipeline(&me->pipeline, in start_pipe()
1475 stage = me->pipeline.stages; in start_pipe()
1477 me->pipeline.current_stage = stage; in start_pipe()
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Dia_css_pipe.h122 struct ia_css_pipeline pipeline; member
160 .pipeline = DEFAULT_PIPELINE, \
Dsh_css_params.c884 struct ia_css_pipeline *pipeline = ia_css_pipe_get_pipeline(pipe); in ia_css_process_kernel() local
888 for (stage = pipeline->stages; stage; stage = stage->next) { in ia_css_process_kernel()
890 process(pipeline->pipe_id, stage, params); in ia_css_process_kernel()
3260 struct ia_css_pipeline *pipeline; in sh_css_param_update_isp_params() local
3266 pipeline = ia_css_pipe_get_pipeline(pipe); in sh_css_param_update_isp_params()
3285 cur_map = &params->pipe_ddr_ptrs[pipeline->pipe_id]; in sh_css_param_update_isp_params()
3286 cur_map_size = &params->pipe_ddr_ptrs_size[pipeline->pipe_id]; in sh_css_param_update_isp_params()
3297 pipeline->stages); in sh_css_param_update_isp_params()
3311 for (stage = pipeline->stages; stage; stage = stage->next) { in sh_css_param_update_isp_params()
3317 process_kernel_parameters(pipeline->pipe_id, in sh_css_param_update_isp_params()
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/drivers/gpu/drm/arm/display/komeda/
Dkomeda_pipeline.c155 return komeda_pipeline_get_first_component(c->pipeline, avail_inputs); in komeda_component_pickup_input()
204 c->pipeline = pipe; in komeda_component_add()
271 struct komeda_pipeline *pipe = c->pipeline; in komeda_component_verify_inputs()
338 return slave ? slave->pipeline : NULL; in komeda_pipeline_get_slave()
Dkomeda_plane.c23 struct komeda_pipeline *pipe = kplane->layer->base.pipeline; in komeda_plane_init_data_flow()
273 get_possible_crtcs(kms, c->pipeline), in komeda_plane_add()
319 komeda_set_crtc_plane_mask(kms, c->pipeline, plane); in komeda_plane_add()
Dkomeda_pipeline_state.c104 WARN_ON(!drm_modeset_is_locked(&c->pipeline->obj.lock)); in komeda_component_get_state()
160 pipe_st = komeda_pipeline_get_state_and_set_crtc(c->pipeline, in komeda_component_get_state_and_set_user()
261 pipe_st = komeda_pipeline_get_state(c->pipeline, state); in komeda_component_get_avail_scaler()
488 struct komeda_pipeline *pipe = scaler->base.pipeline; in komeda_scaler_check_cfg()
595 komeda_split_data_flow(splitter->base.pipeline->scalers[0], in komeda_splitter_validate()
843 struct komeda_scaler *scaler = layer->base.pipeline->scalers[0]; in komeda_complete_data_flow_cfg()
888 struct komeda_pipeline *pipe = layer->base.pipeline; in komeda_build_layer_data_flow()
1091 struct komeda_pipeline *pipe = left->base.pipeline; in komeda_build_layer_split_data_flow()
1159 struct komeda_pipeline *pipe = wb_layer->base.pipeline; in komeda_build_wb_split_data_flow()
/drivers/gpu/drm/sun4i/
Dsun4i_drv.c382 struct device_node *pipeline = of_parse_phandle(np, in sun4i_drv_probe() local
385 if (!pipeline) in sun4i_drv_probe()
388 kfifo_put(&list.fifo, pipeline); in sun4i_drv_probe()
/drivers/staging/media/imx/
DTODO19 pipeline. The controls for each capture device are updated in the
20 link_notify callback when the pipeline is modified. It should be

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