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/drivers/gpu/drm/savage/
Dsavage_state.c290 unsigned int prim = cmd_header->prim.prim; in savage_dispatch_dma_prim() local
291 unsigned int skip = cmd_header->prim.skip; in savage_dispatch_dma_prim()
292 unsigned int n = cmd_header->prim.count; in savage_dispatch_dma_prim()
293 unsigned int start = cmd_header->prim.start; in savage_dispatch_dma_prim()
305 switch (prim) { in savage_dispatch_dma_prim()
308 prim = SAVAGE_PRIM_TRILIST; in savage_dispatch_dma_prim()
327 DRM_ERROR("invalid primitive type %u\n", prim); in savage_dispatch_dma_prim()
379 prim <<= 25; in savage_dispatch_dma_prim()
391 BCI_DRAW_INDICES_S3D(count, prim, start + 2); in savage_dispatch_dma_prim()
401 BCI_DRAW_INDICES_S3D(count, prim, start); in savage_dispatch_dma_prim()
[all …]
/drivers/gpu/drm/mga/
Dmga_drv.h93 drm_mga_primary_buffer_t prim; member
250 if (test_bit(0, &dev_priv->prim.wrapped)) { \
253 } else if (dev_priv->prim.space < \
254 dev_priv->prim.high_mark) { \
264 if (test_bit(0, &dev_priv->prim.wrapped)) { \
280 #define DMA_LOCALS unsigned int write; volatile u8 *prim;
289 dev_priv->prim.space, (n) * DMA_BLOCK_SIZE); \
291 prim = dev_priv->prim.start; \
292 write = dev_priv->prim.tail; \
299 DRM_INFO(" space=0x%x\n", dev_priv->prim.space); \
[all …]
Dmga_dma.c78 drm_mga_primary_buffer_t *primary = &dev_priv->prim; in mga_do_dma_reset()
105 drm_mga_primary_buffer_t *primary = &dev_priv->prim; in mga_do_dma_flush()
160 drm_mga_primary_buffer_t *primary = &dev_priv->prim; in mga_do_dma_wrap_start()
200 drm_mga_primary_buffer_t *primary = &dev_priv->prim; in mga_do_dma_wrap_end()
900 dev_priv->prim.status = (u32 *) dev_priv->status->handle; in mga_do_init_dma()
908 …MGA_WRITE(MGA_PRIMPTR, virt_to_bus((void *)dev_priv->prim.status) | MGA_PRIMPTREN0 | /* Soft trap,… in mga_do_init_dma()
912 dev_priv->prim.start = (u8 *) dev_priv->primary->handle; in mga_do_init_dma()
913 dev_priv->prim.end = ((u8 *) dev_priv->primary->handle in mga_do_init_dma()
915 dev_priv->prim.size = dev_priv->primary->size; in mga_do_init_dma()
917 dev_priv->prim.tail = 0; in mga_do_init_dma()
[all …]
Dmga_state.c579 sarea_priv->last_frame.head = dev_priv->prim.tail; in mga_dma_dispatch_swap()
580 sarea_priv->last_frame.wrap = dev_priv->prim.last_wrap; in mga_dma_dispatch_swap()
/drivers/powercap/
Dintel_rapl_common.c133 enum rapl_primitives prim,
136 enum rapl_primitives prim,
362 int prim; in get_current_power_limit() local
376 prim = POWER_LIMIT1; in get_current_power_limit()
379 prim = POWER_LIMIT2; in get_current_power_limit()
382 prim = POWER_LIMIT4; in get_current_power_limit()
388 if (rapl_read_data_raw(rd, prim, true, &val)) in get_current_power_limit()
491 int prim; in get_max_power() local
498 prim = THERMAL_SPEC_POWER; in get_max_power()
501 prim = MAX_POWER; in get_max_power()
[all …]
/drivers/gpu/drm/r128/
Dr128_state.c579 int prim = buf_priv->prim; in r128_cce_dispatch_vertex() local
608 OUT_RING(prim | R128_CCE_VC_CNTL_PRIM_WALK_LIST | in r128_cce_dispatch_vertex()
704 int prim = buf_priv->prim; in r128_cce_dispatch_indices() local
731 data[4] = cpu_to_le32((prim | R128_CCE_VC_CNTL_PRIM_WALK_IND | in r128_cce_dispatch_indices()
1334 if (vertex->prim < 0 || in r128_cce_vertex()
1335 vertex->prim > R128_CCE_VC_CNTL_PRIM_TYPE_TRI_TYPE2) { in r128_cce_vertex()
1336 DRM_ERROR("buffer prim %d\n", vertex->prim); in r128_cce_vertex()
1357 buf_priv->prim = vertex->prim; in r128_cce_vertex()
1387 if (elts->prim < 0 || in r128_cce_indices()
1388 elts->prim > R128_CCE_VC_CNTL_PRIM_TYPE_TRI_TYPE2) { in r128_cce_indices()
[all …]
Dr128_drv.h138 int prim; member
/drivers/isdn/mISDN/
Ddsp_core.c673 switch (hh->prim) { in dsp_function()
706 hh->prim = DL_DATA_IND; in dsp_function()
765 hh->prim = DL_DATA_IND; in dsp_function()
852 hh->prim = DL_ESTABLISH_CNF; in dsp_function()
868 hh->prim = DL_RELEASE_CNF; in dsp_function()
885 hh->prim = PH_DATA_REQ; in dsp_function()
916 hh->prim = PH_ACTIVATE_REQ; in dsp_function()
936 hh->prim = PH_DEACTIVATE_REQ; in dsp_function()
943 __func__, hh->prim, dsp->name); in dsp_function()
1026 if (hh->prim == DL_DATA_REQ) { in dsp_send_bh()
Dlayer2.c138 l2up(struct layer2 *l2, u_int prim, struct sk_buff *skb) in l2up() argument
144 mISDN_HEAD_PRIM(skb) = prim; in l2up()
155 l2up_create(struct layer2 *l2, u_int prim, int len, void *arg) in l2up_create() argument
167 hh->prim = prim; in l2up_create()
195 if (hh->prim == PH_DATA_REQ) { in l2down_raw()
206 l2down(struct layer2 *l2, u_int prim, u_int id, struct sk_buff *skb) in l2down() argument
210 hh->prim = prim; in l2down()
216 l2down_create(struct layer2 *l2, u_int prim, u_int id, int len, void *arg) in l2down_create() argument
226 hh->prim = prim; in l2down_create()
292 hh->prim = event == EV_L2_T200 ? DL_TIMER200_IND : DL_TIMER203_IND; in l2_timeout()
[all …]
Dstack.c27 __func__, hh->prim, hh->id, skb); in _queue_message()
108 hh->prim, ch->addr, ret); in send_layer2()
132 __func__, hh->prim, ret); in send_layer2()
146 lm = hh->prim & MISDN_LAYERMASK; in send_msg_to_layer()
149 __func__, hh->prim, hh->id, skb); in send_msg_to_layer()
168 __func__, dev_name(&st->dev->dev), hh->prim, in send_msg_to_layer()
178 __func__, dev_name(&st->dev->dev), hh->prim, in send_msg_to_layer()
183 __func__, dev_name(&st->dev->dev), hh->prim); in send_msg_to_layer()
Dhwchannel.c221 hh->prim = PH_DATA_IND; in recv_Dchannel()
240 hh->prim = PH_DATA_E_IND; in recv_Echannel()
267 hh->prim = PH_DATA_IND; in recv_Bchannel()
393 hh->prim = pr; in queue_ch_frame()
Dtei.c293 teiup_create(struct manager *mgr, u_int prim, int len, void *arg) in teiup_create() argument
303 hh->prim = prim; in teiup_create()
1105 __func__, hh->prim, hh->id); in mgr_send()
1106 switch (hh->prim) { in mgr_send()
1205 __func__, hh->prim, hh->id); in check_data()
1208 if (hh->prim != PH_DATA_IND) in check_data()
1310 hhc->prim = DL_INTERN_MSG; in mgr_bcast()
1319 hh->prim, l2->ch.addr, ret); in mgr_bcast()
Ddsp_cmx.c1362 hh->prim = PH_DATA_REQ;
1581 hh->prim = DL_DATA_REQ;
1596 thh->prim = DL_DATA_REQ;
1937 hh->prim = PH_DATA_REQ;
1953 hh->prim = PH_DATA_REQ;
Dl1oip_core.c876 switch (hh->prim) { in handle_dmsg()
1095 switch (hh->prim) { in handle_bmsg()
/drivers/scsi/libsas/
Dsas_port.c277 u32 prim; in sas_porte_broadcast_rcvd() local
280 prim = phy->sas_prim; in sas_porte_broadcast_rcvd()
283 pr_debug("broadcast received: %d\n", prim); in sas_porte_broadcast_rcvd()
/drivers/isdn/hardware/mISDN/
Dw6692.c940 switch (hh->prim) { in w6692_l2l1B()
972 card->name, __func__, hh->prim, hh->id); in w6692_l2l1B()
1067 switch (hh->prim) { in w6692_l2l1D()
1081 ret = l1_event(dch->l1, hh->prim); in w6692_l2l1D()
1085 ret = l1_event(dch->l1, hh->prim); in w6692_l2l1D()
DmISDNipac.c562 switch (hh->prim) { in isac_l1hw()
576 ret = l1_event(dch->l1, hh->prim); in isac_l1hw()
580 ret = l1_event(dch->l1, hh->prim); in isac_l1hw()
1339 switch (hh->prim) { in hscx_l2l1()
1371 hx->ip->name, __func__, hh->prim, hh->id); in hscx_l2l1()
Dhfcsusb.c207 switch (hh->prim) { in hfcusb_l2l1B()
283 switch (hh->prim) { in hfcusb_l2l1D()
318 ret = l1_event(dch->l1, hh->prim); in hfcusb_l2l1D()
353 ret = l1_event(dch->l1, hh->prim); in hfcusb_l2l1D()
Dhfcpci.c1583 switch (hh->prim) { in hfcpci_l2l1D()
1613 ret = l1_event(dch->l1, hh->prim); in hfcpci_l2l1D()
1648 ret = l1_event(dch->l1, hh->prim); in hfcpci_l2l1D()
1670 switch (hh->prim) { in hfcpci_l2l1B()
DmISDNisar.c1475 switch (hh->prim) { in isar_l2l1()
1554 ich->is->name, __func__, hh->prim, hh->id); in isar_l2l1()
Dhfcmulti.c1913 hh->prim = PH_CONTROL_IND; in hfcmulti_dtmf()
3338 switch (hh->prim) { in handle_dmsg()
3387 ret = l1_event(dch->l1, hh->prim); in handle_dmsg()
3437 ret = l1_event(dch->l1, hh->prim); in handle_dmsg()
3469 switch (hh->prim) { in handle_bmsg()
/drivers/net/bonding/
Dbond_main.c992 struct slave *prim = rtnl_dereference(bond->primary_slave); in bond_choose_primary_or_current() local
995 if (!prim || prim->link != BOND_LINK_UP) { in bond_choose_primary_or_current()
1003 return prim; in bond_choose_primary_or_current()
1007 return prim; in bond_choose_primary_or_current()
1012 return prim; in bond_choose_primary_or_current()
1014 if (prim->speed < curr->speed) in bond_choose_primary_or_current()
1016 if (prim->speed == curr->speed && prim->duplex <= curr->duplex) in bond_choose_primary_or_current()
1018 return prim; in bond_choose_primary_or_current()
/drivers/macintosh/
Dvia-pmu.c539 struct device_node* prim = in via_pmu_dev_init() local
542 if (prim) in via_pmu_dev_init()
543 prim_info = of_get_property(prim, "prim-info", NULL); in via_pmu_dev_init()
551 of_node_put(prim); in via_pmu_dev_init()
/drivers/scsi/aic94xx/
Daic94xx_sas.h544 u8 prim[4]; /* K, D0, D1, D2 */ member
/drivers/gpu/drm/i810/
Di810_dma.c738 unsigned int prim = (sarea_priv->vertex_prim & PR_MASK); in i810_dma_dispatch_vertex() local
741 ((GFX_OP_PRIMITIVE | prim | ((used / 4) - 2))); in i810_dma_dispatch_vertex()

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