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Searched refs:ramht (Results 1 – 23 of 23) sorted by relevance

/drivers/gpu/drm/nouveau/nvkm/core/
Dramht.c27 nvkm_ramht_hash(struct nvkm_ramht *ramht, int chid, u32 handle) in nvkm_ramht_hash() argument
32 hash ^= (handle & ((1 << ramht->bits) - 1)); in nvkm_ramht_hash()
33 handle >>= ramht->bits; in nvkm_ramht_hash()
36 hash ^= chid << (ramht->bits - 4); in nvkm_ramht_hash()
41 nvkm_ramht_search(struct nvkm_ramht *ramht, int chid, u32 handle) in nvkm_ramht_search() argument
45 co = ho = nvkm_ramht_hash(ramht, chid, handle); in nvkm_ramht_search()
47 if (ramht->data[co].chid == chid) { in nvkm_ramht_search()
48 if (ramht->data[co].handle == handle) in nvkm_ramht_search()
49 return ramht->data[co].inst; in nvkm_ramht_search()
52 if (++co >= ramht->size) in nvkm_ramht_search()
[all …]
DKbuild15 nvkm-y += nvkm/core/ramht.o
/drivers/gpu/drm/nouveau/nvkm/engine/fifo/
Dnv17.c56 struct nvkm_ramht *ramht = imem->ramht; in nv17_fifo_init() local
64 ((ramht->bits - 9) << 16) | in nv17_fifo_init()
65 (ramht->gpuobj->addr >> 8)); in nv17_fifo_init()
Dnv40.c66 struct nvkm_ramht *ramht = imem->ramht; in nv40_fifo_init() local
75 ((ramht->bits - 9) << 16) | in nv40_fifo_init()
76 (ramht->gpuobj->addr >> 8)); in nv40_fifo_init()
Dchannv50.c154 nvkm_ramht_remove(chan->ramht, cookie); in nv50_fifo_chan_object_dtor()
175 return nvkm_ramht_insert(chan->ramht, object, 0, 4, handle, context); in nv50_fifo_chan_object_ctor()
209 nvkm_ramht_del(&chan->ramht); in nv50_fifo_chan_dtor()
267 return nvkm_ramht_new(device, 0x8000, 16, chan->base.inst, &chan->ramht); in nv50_fifo_chan_ctor()
Ddmanv50.c79 nvkm_wo32(chan->ramfc, 0x80, ((chan->ramht->bits - 9) << 27) | in nv50_fifo_dma_new()
81 (chan->ramht->gpuobj->node->offset >> 4)); in nv50_fifo_dma_new()
Dgpfifonv50.c80 nvkm_wo32(chan->ramfc, 0x80, ((chan->ramht->bits - 9) << 27) | in nv50_fifo_gpfifo_new()
82 (chan->ramht->gpuobj->node->offset >> 4)); in nv50_fifo_gpfifo_new()
Dnv04.c304 struct nvkm_ramht *ramht = imem->ramht; in nv04_fifo_init() local
312 ((ramht->bits - 9) << 16) | in nv04_fifo_init()
313 (ramht->gpuobj->addr >> 8)); in nv04_fifo_init()
Dgpfifog84.c80 nvkm_wo32(chan->ramfc, 0x80, ((chan->ramht->bits - 9) << 27) | in g84_fifo_gpfifo_new()
82 (chan->ramht->gpuobj->node->offset >> 4)); in g84_fifo_gpfifo_new()
Ddmag84.c79 nvkm_wo32(chan->ramfc, 0x80, ((chan->ramht->bits - 9) << 27) | in g84_fifo_dma_new()
81 (chan->ramht->gpuobj->node->offset >> 4)); in g84_fifo_dma_new()
Dchannv50.h16 struct nvkm_ramht *ramht; member
Dchang84.c201 return nvkm_ramht_insert(chan->ramht, object, 0, 4, handle, context); in g84_fifo_chan_object_ctor()
283 return nvkm_ramht_new(device, 0x8000, 16, chan->base.inst, &chan->ramht); in g84_fifo_chan_ctor()
Ddmanv04.c42 nvkm_ramht_remove(imem->ramht, cookie); in nv04_fifo_dma_object_dtor()
67 hash = nvkm_ramht_insert(imem->ramht, object, chan->base.chid, 4, in nv04_fifo_dma_object_ctor()
Ddmanv40.c163 hash = nvkm_ramht_insert(imem->ramht, object, chan->base.chid, 4, in nv40_fifo_dma_object_ctor()
/drivers/gpu/drm/nouveau/nvkm/subdev/instmem/
Dnv04.c179 ret = nvkm_ramht_new(device, 0x08000, 0, NULL, &imem->base.ramht); in nv04_instmem_oneinit()
204 nvkm_ramht_del(&imem->base.ramht); in nv04_instmem_dtor()
Dnv40.c191 ret = nvkm_ramht_new(device, 0x08000, 0, NULL, &imem->base.ramht); in nv40_instmem_oneinit()
220 nvkm_ramht_del(&imem->base.ramht); in nv40_instmem_dtor()
/drivers/gpu/drm/nouveau/include/nvkm/subdev/
Dinstmem.h17 struct nvkm_ramht *ramht; member
/drivers/gpu/drm/nouveau/nvkm/engine/disp/
Ddmacgf119.c33 return nvkm_ramht_insert(chan->disp->ramht, object, in gf119_disp_dmac_bind()
Dnv50.h38 struct nvkm_ramht *ramht; member
Ddmacgv100.c44 return nvkm_ramht_insert(chan->disp->ramht, object, in gv100_disp_dmac_bind()
Ddmacnv50.c73 return nvkm_ramht_insert(chan->disp->ramht, object, in nv50_disp_dmac_bind()
Dnv50.c71 nvkm_ramht_del(&disp->ramht); in nv50_disp_dtor_()
142 0x1000, 0, disp->inst, &disp->ramht); in nv50_disp_oneinit_()
Dchannv50.c235 nvkm_ramht_remove(object->disp->ramht, object->hash); in nv50_disp_chan_child_del_()