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Searched refs:reg_num (Results 1 – 25 of 110) sorted by relevance

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/drivers/gpu/drm/amd/display/dc/irq/dce120/
Dirq_service_dce120.c105 #define IRQ_REG_ENTRY(block, reg_num, reg1, mask1, reg2, mask2)\ argument
106 .enable_reg = SRI(reg1, block, reg_num),\
108 block ## reg_num ## _ ## reg1 ## __ ## mask1 ## _MASK,\
110 block ## reg_num ## _ ## reg1 ## __ ## mask1 ## _MASK,\
111 ~block ## reg_num ## _ ## reg1 ## __ ## mask1 ## _MASK \
113 .ack_reg = SRI(reg2, block, reg_num),\
115 block ## reg_num ## _ ## reg2 ## __ ## mask2 ## _MASK,\
117 block ## reg_num ## _ ## reg2 ## __ ## mask2 ## _MASK \
119 #define hpd_int_entry(reg_num)\ argument
120 [DC_IRQ_SOURCE_HPD1 + reg_num] = {\
[all …]
/drivers/gpu/drm/amd/display/dc/irq/dce80/
Dirq_service_dce80.c94 #define hpd_int_entry(reg_num)\ argument
95 [DC_IRQ_SOURCE_INVALID + reg_num] = {\
96 .enable_reg = mmDC_HPD ## reg_num ## _INT_CONTROL,\
102 .ack_reg = mmDC_HPD ## reg_num ## _INT_CONTROL,\
105 .status_reg = mmDC_HPD ## reg_num ## _INT_STATUS,\
109 #define hpd_rx_int_entry(reg_num)\ argument
110 [DC_IRQ_SOURCE_HPD6 + reg_num] = {\
111 .enable_reg = mmDC_HPD ## reg_num ## _INT_CONTROL,\
116 .ack_reg = mmDC_HPD ## reg_num ## _INT_CONTROL,\
119 .status_reg = mmDC_HPD ## reg_num ## _INT_STATUS,\
[all …]
/drivers/gpu/drm/amd/display/dc/irq/dcn20/
Dirq_service_dcn20.c188 #define IRQ_REG_ENTRY(block, reg_num, reg1, mask1, reg2, mask2)\ argument
189 .enable_reg = SRI(reg1, block, reg_num),\
191 block ## reg_num ## _ ## reg1 ## __ ## mask1 ## _MASK,\
193 block ## reg_num ## _ ## reg1 ## __ ## mask1 ## _MASK,\
194 ~block ## reg_num ## _ ## reg1 ## __ ## mask1 ## _MASK \
196 .ack_reg = SRI(reg2, block, reg_num),\
198 block ## reg_num ## _ ## reg2 ## __ ## mask2 ## _MASK,\
200 block ## reg_num ## _ ## reg2 ## __ ## mask2 ## _MASK \
204 #define hpd_int_entry(reg_num)\ argument
205 [DC_IRQ_SOURCE_HPD1 + reg_num] = {\
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/drivers/gpu/drm/amd/display/dc/irq/dcn10/
Dirq_service_dcn10.c186 #define IRQ_REG_ENTRY(block, reg_num, reg1, mask1, reg2, mask2)\ argument
187 .enable_reg = SRI(reg1, block, reg_num),\
189 block ## reg_num ## _ ## reg1 ## __ ## mask1 ## _MASK,\
191 block ## reg_num ## _ ## reg1 ## __ ## mask1 ## _MASK,\
192 ~block ## reg_num ## _ ## reg1 ## __ ## mask1 ## _MASK \
194 .ack_reg = SRI(reg2, block, reg_num),\
196 block ## reg_num ## _ ## reg2 ## __ ## mask2 ## _MASK,\
198 block ## reg_num ## _ ## reg2 ## __ ## mask2 ## _MASK \
200 #define hpd_int_entry(reg_num)\ argument
201 [DC_IRQ_SOURCE_HPD1 + reg_num] = {\
[all …]
/drivers/gpu/drm/amd/display/dc/irq/dcn30/
Dirq_service_dcn30.c195 #define IRQ_REG_ENTRY(block, reg_num, reg1, mask1, reg2, mask2)\ argument
196 .enable_reg = SRI(reg1, block, reg_num),\
198 block ## reg_num ## _ ## reg1 ## __ ## mask1 ## _MASK,\
200 block ## reg_num ## _ ## reg1 ## __ ## mask1 ## _MASK,\
201 ~block ## reg_num ## _ ## reg1 ## __ ## mask1 ## _MASK \
203 .ack_reg = SRI(reg2, block, reg_num),\
205 block ## reg_num ## _ ## reg2 ## __ ## mask2 ## _MASK,\
207 block ## reg_num ## _ ## reg2 ## __ ## mask2 ## _MASK \
211 #define hpd_int_entry(reg_num)\ argument
212 [DC_IRQ_SOURCE_HPD1 + reg_num] = {\
[all …]
/drivers/gpu/drm/amd/display/dc/irq/dcn21/
Dirq_service_dcn21.c189 #define IRQ_REG_ENTRY(block, reg_num, reg1, mask1, reg2, mask2)\ argument
190 .enable_reg = SRI(reg1, block, reg_num),\
192 block ## reg_num ## _ ## reg1 ## __ ## mask1 ## _MASK,\
194 block ## reg_num ## _ ## reg1 ## __ ## mask1 ## _MASK,\
195 ~block ## reg_num ## _ ## reg1 ## __ ## mask1 ## _MASK \
197 .ack_reg = SRI(reg2, block, reg_num),\
199 block ## reg_num ## _ ## reg2 ## __ ## mask2 ## _MASK,\
201 block ## reg_num ## _ ## reg2 ## __ ## mask2 ## _MASK \
205 #define hpd_int_entry(reg_num)\ argument
206 [DC_IRQ_SOURCE_HPD1 + reg_num] = {\
[all …]
/drivers/gpu/drm/amd/display/dc/irq/dce60/
Dirq_service_dce60.c101 #define hpd_int_entry(reg_num)\ argument
102 [DC_IRQ_SOURCE_INVALID + reg_num] = {\
103 .enable_reg = mmDC_HPD ## reg_num ## _INT_CONTROL,\
109 .ack_reg = mmDC_HPD ## reg_num ## _INT_CONTROL,\
112 .status_reg = mmDC_HPD ## reg_num ## _INT_STATUS,\
116 #define hpd_rx_int_entry(reg_num)\ argument
117 [DC_IRQ_SOURCE_HPD6 + reg_num] = {\
118 .enable_reg = mmDC_HPD ## reg_num ## _INT_CONTROL,\
123 .ack_reg = mmDC_HPD ## reg_num ## _INT_CONTROL,\
126 .status_reg = mmDC_HPD ## reg_num ## _INT_STATUS,\
[all …]
/drivers/gpu/drm/amd/display/dc/irq/dce110/
Dirq_service_dce110.c91 #define hpd_int_entry(reg_num)\ argument
92 [DC_IRQ_SOURCE_HPD1 + reg_num] = {\
93 .enable_reg = mmHPD ## reg_num ## _DC_HPD_INT_CONTROL,\
99 .ack_reg = mmHPD ## reg_num ## _DC_HPD_INT_CONTROL,\
102 .status_reg = mmHPD ## reg_num ## _DC_HPD_INT_STATUS,\
106 #define hpd_rx_int_entry(reg_num)\ argument
107 [DC_IRQ_SOURCE_HPD1RX + reg_num] = {\
108 .enable_reg = mmHPD ## reg_num ## _DC_HPD_INT_CONTROL,\
113 .ack_reg = mmHPD ## reg_num ## _DC_HPD_INT_CONTROL,\
116 .status_reg = mmHPD ## reg_num ## _DC_HPD_INT_STATUS,\
[all …]
/drivers/video/fbdev/via/
Dhw.h355 int reg_num; member
361 int reg_num; member
367 int reg_num; member
373 int reg_num; member
379 int reg_num; member
385 int reg_num; member
391 int reg_num; member
397 int reg_num; member
403 int reg_num; member
409 int reg_num; member
[all …]
Dvt1636.c69 int reg_num, i; in viafb_init_lvds_vt1636() local
72 reg_num = ARRAY_SIZE(common_init_data); in viafb_init_lvds_vt1636()
73 for (i = 0; i < reg_num; i++) in viafb_init_lvds_vt1636()
Dhw.c1022 iga1_fetch_count_reg.reg_num; in viafb_load_fetch_count_reg()
1029 iga2_fetch_count_reg.reg_num; in viafb_load_fetch_count_reg()
1161 display_fifo_depth_reg.iga1_fifo_depth_select_reg.reg_num; in viafb_load_FIFO_reg()
1169 iga1_fifo_threshold_select_reg.reg_num; in viafb_load_FIFO_reg()
1180 iga1_fifo_high_threshold_select_reg.reg_num; in viafb_load_FIFO_reg()
1192 iga1_display_queue_expire_num_reg.reg_num; in viafb_load_FIFO_reg()
1315 iga2_fifo_depth_select_reg.reg_num; in viafb_load_FIFO_reg()
1328 iga2_fifo_depth_select_reg.reg_num; in viafb_load_FIFO_reg()
1340 iga2_fifo_threshold_select_reg.reg_num; in viafb_load_FIFO_reg()
1351 iga2_fifo_high_threshold_select_reg.reg_num; in viafb_load_FIFO_reg()
[all …]
/drivers/irqchip/
Dirq-imx-irqsteer.c33 int reg_num; member
42 return (data->reg_num - irqnum / 32 - 1); in imx_irqsteer_get_reg_index()
53 val = readl_relaxed(data->regs + CHANMASK(idx, data->reg_num)); in imx_irqsteer_irq_unmask()
55 writel_relaxed(val, data->regs + CHANMASK(idx, data->reg_num)); in imx_irqsteer_irq_unmask()
67 val = readl_relaxed(data->regs + CHANMASK(idx, data->reg_num)); in imx_irqsteer_irq_mask()
69 writel_relaxed(val, data->regs + CHANMASK(idx, data->reg_num)); in imx_irqsteer_irq_mask()
127 if (hwirq >= data->reg_num * 32) in imx_irqsteer_irq_handler()
131 CHANSTATUS(idx, data->reg_num)); in imx_irqsteer_irq_handler()
179 data->reg_num = irqs_num / 32; in imx_irqsteer_probe()
183 sizeof(u32) * data->reg_num, in imx_irqsteer_probe()
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/drivers/net/ethernet/arc/
Demac_mdio.c56 static int arc_mdio_read(struct mii_bus *bus, int phy_addr, int reg_num) in arc_mdio_read() argument
63 0x60020000 | (phy_addr << 23) | (reg_num << 18)); in arc_mdio_read()
72 phy_addr, reg_num, value); in arc_mdio_read()
89 int reg_num, u16 value) in arc_mdio_write() argument
95 phy_addr, reg_num, value); in arc_mdio_write()
98 0x50020000 | (phy_addr << 23) | (reg_num << 18) | value); in arc_mdio_write()
/drivers/input/keyboard/
Dbcm-keypad.c103 static void bcm_kp_report_keys(struct bcm_kp *kp, int reg_num, int pull_mode) in bcm_kp_report_keys() argument
112 writel(0xFFFFFFFF, kp->base + KPICRN_OFFSET(reg_num)); in bcm_kp_report_keys()
114 state = readl(kp->base + KPSSRN_OFFSET(reg_num)); in bcm_kp_report_keys()
115 change = kp->last_state[reg_num] ^ state; in bcm_kp_report_keys()
116 kp->last_state[reg_num] = state; in bcm_kp_report_keys()
122 row = BIT_TO_ROW_SSRN(bit_nr, reg_num); in bcm_kp_report_keys()
133 int reg_num; in bcm_kp_isr_thread() local
135 for (reg_num = 0; reg_num <= 1; reg_num++) in bcm_kp_isr_thread()
136 bcm_kp_report_keys(kp, reg_num, pull_mode); in bcm_kp_isr_thread()
/drivers/crypto/qat/qat_common/
Dqat_hal.c224 unsigned short reg_num) in qat_hal_get_reg_addr() argument
231 reg_addr = 0x80 | (reg_num & 0x7f); in qat_hal_get_reg_addr()
235 reg_addr = reg_num & 0x1f; in qat_hal_get_reg_addr()
240 reg_addr = 0x180 | (reg_num & 0x1f); in qat_hal_get_reg_addr()
243 reg_addr = 0x140 | ((reg_num & 0x3) << 1); in qat_hal_get_reg_addr()
248 reg_addr = 0x1c0 | (reg_num & 0x1f); in qat_hal_get_reg_addr()
251 reg_addr = 0x100 | ((reg_num & 0x3) << 1); in qat_hal_get_reg_addr()
254 reg_addr = 0x280 | (reg_num & 0x1f); in qat_hal_get_reg_addr()
263 reg_addr = 0x300 | (reg_num & 0xff); in qat_hal_get_reg_addr()
929 unsigned short reg_num, unsigned int *data) in qat_hal_rd_rel_reg() argument
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Dadf_common_drv.h168 unsigned short reg_num, unsigned int regdata);
172 unsigned short reg_num, unsigned int regdata);
176 unsigned short reg_num, unsigned int regdata);
179 unsigned short reg_num, unsigned int regdata);
/drivers/w1/
Dw1.c100 ssize_t count = sizeof(sl->reg_num); in id_show()
102 memcpy(buf, (u8 *)&sl->reg_num, count); in id_show()
446 if (sl->reg_num.family == rn->family && in w1_slave_search_device()
447 sl->reg_num.id == rn->id && in w1_slave_search_device()
448 sl->reg_num.crc == rn->crc) { in w1_slave_search_device()
604 err = add_uevent_var(env, "W1_FID=%02X", sl->reg_num.family); in w1_uevent()
609 (unsigned long long)sl->reg_num.id); in w1_uevent()
685 (unsigned int) sl->reg_num.family, in __w1_attach_slave_device()
686 (unsigned long long) sl->reg_num.id); in __w1_attach_slave_device()
689 (unsigned int) sl->reg_num.family, in __w1_attach_slave_device()
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/drivers/soc/fsl/qe/
Ducc.c89 unsigned int *reg_num, unsigned int *shift) in get_cmxucr_reg() argument
93 *reg_num = cmx + 1; in get_cmxucr_reg()
101 unsigned int reg_num; in ucc_mux_set_grant_tsa_bkpt() local
108 get_cmxucr_reg(ucc_num, &cmxucr, &reg_num, &shift); in ucc_mux_set_grant_tsa_bkpt()
122 unsigned int reg_num; in ucc_set_qe_mux_rxtx() local
134 get_cmxucr_reg(ucc_num, &cmxucr, &reg_num, &shift); in ucc_set_qe_mux_rxtx()
136 switch (reg_num) { in ucc_set_qe_mux_rxtx()
/drivers/gpu/drm/amd/display/dc/
Ddm_services.h183 #define get_reg_field_value_soc15(reg_value, block, reg_num, reg_name, reg_field)\ argument
186 block ## reg_num ## _ ## reg_name ## __ ## reg_field ## _MASK,\
187 block ## reg_num ## _ ## reg_name ## __ ## reg_field ## __SHIFT)
189 #define set_reg_field_value_soc15(reg_value, value, block, reg_num, reg_name, reg_field)\ argument
193 block ## reg_num ## _ ## reg_name ## __ ## reg_field ## _MASK,\
194 block ## reg_num ## _ ## reg_name ## __ ## reg_field ## __SHIFT)
/drivers/staging/media/hantro/
Dhantro_g1_h264_dec.c135 int reg_num; in set_ref() local
182 reg_num = 0; in set_ref()
190 vdpu_write_relaxed(vpu, reg, G1_REG_BD_REF_PIC(reg_num++)); in set_ref()
210 reg_num = 0; in set_ref()
218 vdpu_write_relaxed(vpu, reg, G1_REG_FWD_PIC(reg_num++)); in set_ref()
/drivers/mfd/
Dezx-pcap.c77 int ezx_pcap_write(struct pcap_chip *pcap, u8 reg_num, u32 value) in ezx_pcap_write() argument
85 | (reg_num << PCAP_REGISTER_ADDRESS_SHIFT); in ezx_pcap_write()
93 int ezx_pcap_read(struct pcap_chip *pcap, u8 reg_num, u32 *value) in ezx_pcap_read() argument
100 | (reg_num << PCAP_REGISTER_ADDRESS_SHIFT); in ezx_pcap_read()
109 int ezx_pcap_set_bits(struct pcap_chip *pcap, u8 reg_num, u32 mask, u32 val) in ezx_pcap_set_bits() argument
114 (reg_num << PCAP_REGISTER_ADDRESS_SHIFT); in ezx_pcap_set_bits()
123 (reg_num << PCAP_REGISTER_ADDRESS_SHIFT); in ezx_pcap_set_bits()
/drivers/w1/slaves/
Dw1_ds250x.c203 sl->master->bus_master->dev_id, sl->reg_num.family, in w1_eprom_add_slave()
204 (unsigned long long)sl->reg_num.id); in w1_eprom_add_slave()
208 sl->reg_num.family, in w1_eprom_add_slave()
209 (unsigned long long)sl->reg_num.id); in w1_eprom_add_slave()
Dw1_ds2405.c30 u64 dev_addr = le64_to_cpu(*(u64 *)&sl->reg_num); in w1_ds2405_select()
182 u64 dev_addr = le64_to_cpu(*(u64 *)&sl->reg_num); in output_store()
/drivers/media/i2c/
Dov7740.c133 u32 reg_num; member
140 u32 reg_num; member
265 .reg_num = ARRAY_SIZE(ov7740_vga),
598 ov7740->fmt->reg_num); in ov7740_start_streaming()
606 ov7740->frmsize->reg_num); in ov7740_start_streaming()
700 .reg_num = ARRAY_SIZE(ov7740_format_yuyv),
706 .reg_num = ARRAY_SIZE(ov7740_format_bggr8),
/drivers/net/phy/
Dfixed_phy.c73 static int fixed_mdio_read(struct mii_bus *bus, int phy_addr, int reg_num) in fixed_mdio_read() argument
93 return swphy_read_reg(reg_num, &state); in fixed_mdio_read()
100 static int fixed_mdio_write(struct mii_bus *bus, int phy_addr, int reg_num, in fixed_mdio_write() argument

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