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Searched refs:regbase (Results 1 – 25 of 47) sorted by relevance

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/drivers/video/fbdev/
Dwmt_ge_rops.c39 static void __iomem *regbase; variable
60 (p->var.bits_per_pixel == 8 ? 0 : 1), regbase + GE_DEPTH_OFF); in wmt_ge_fillrect()
61 writel(p->var.bits_per_pixel == 15 ? 1 : 0, regbase + GE_HIGHCOLOR_OFF); in wmt_ge_fillrect()
62 writel(p->fix.smem_start, regbase + GE_DESTBASE_OFF); in wmt_ge_fillrect()
63 writel(p->var.xres_virtual - 1, regbase + GE_DESTDISPW_OFF); in wmt_ge_fillrect()
64 writel(p->var.yres_virtual - 1, regbase + GE_DESTDISPH_OFF); in wmt_ge_fillrect()
65 writel(rect->dx, regbase + GE_DESTAREAX_OFF); in wmt_ge_fillrect()
66 writel(rect->dy, regbase + GE_DESTAREAY_OFF); in wmt_ge_fillrect()
67 writel(rect->width - 1, regbase + GE_DESTAREAW_OFF); in wmt_ge_fillrect()
68 writel(rect->height - 1, regbase + GE_DESTAREAH_OFF); in wmt_ge_fillrect()
[all …]
Dcirrusfb.c355 u8 __iomem *regbase; member
395 static void cirrusfb_WaitBLT(u8 __iomem *regbase);
396 static void cirrusfb_BitBLT(u8 __iomem *regbase, int bits_per_pixel,
401 static void cirrusfb_RectFill(u8 __iomem *regbase, int bits_per_pixel,
410 static void cirrusfb_dbg_reg_dump(struct fb_info *info, caddr_t regbase);
412 caddr_t regbase,
451 long mclk = vga_rseq(cinfo->regbase, CL_SEQR1F) & 0x3f; in cirrusfb_check_mclk()
637 old1f = vga_rseq(cinfo->regbase, CL_SEQR1F) & ~0x40; in cirrusfb_set_mclk_as_source()
643 old1e = vga_rseq(cinfo->regbase, CL_SEQR1E) & ~0x1; in cirrusfb_set_mclk_as_source()
647 vga_wseq(cinfo->regbase, CL_SEQR1E, old1e); in cirrusfb_set_mclk_as_source()
[all …]
Dwm8505fb.c38 void __iomem *regbase; member
51 writel(0, fbi->regbase + i); in wm8505fb_init_hw()
54 writel(fbi->fb.fix.smem_start, fbi->regbase + WMT_GOVR_FBADDR); in wm8505fb_init_hw()
55 writel(fbi->fb.fix.smem_start, fbi->regbase + WMT_GOVR_FBADDR1); in wm8505fb_init_hw()
62 writel(0x31c, fbi->regbase + WMT_GOVR_COLORSPACE); in wm8505fb_init_hw()
63 writel(1, fbi->regbase + WMT_GOVR_COLORSPACE1); in wm8505fb_init_hw()
66 writel(info->var.xres, fbi->regbase + WMT_GOVR_XRES); in wm8505fb_init_hw()
67 writel(info->var.xres_virtual, fbi->regbase + WMT_GOVR_XRES_VIRTUAL); in wm8505fb_init_hw()
70 writel(0xf, fbi->regbase + WMT_GOVR_FHI); in wm8505fb_init_hw()
71 writel(4, fbi->regbase + WMT_GOVR_DVO_SET); in wm8505fb_init_hw()
[all …]
Dvt8500lcdfb.c112 control0 = readl(fbi->regbase) & ~0xf; in vt8500lcd_set_par()
113 writel(0, fbi->regbase); in vt8500lcd_set_par()
114 while (readl(fbi->regbase + 0x38) & 0x10) in vt8500lcd_set_par()
119 | (info->var.right_margin & 0xff), fbi->regbase + 0x4); in vt8500lcd_set_par()
123 | (info->var.lower_margin & 0xff), fbi->regbase + 0x8); in vt8500lcd_set_par()
125 | ((info->var.xres - 1) & 0x400), fbi->regbase + 0x10); in vt8500lcd_set_par()
126 writel(0x80000000, fbi->regbase + 0x20); in vt8500lcd_set_par()
127 writel(control0 | (reg_bpp << 1) | 0x100, fbi->regbase); in vt8500lcd_set_par()
186 writel(0xffffffff ^ (1 << 3), fbi->regbase + 0x3c); in vt8500lcd_ioctl()
188 readl(fbi->regbase + 0x38) & (1 << 3), HZ / 10); in vt8500lcd_ioctl()
[all …]
/drivers/staging/comedi/drivers/
Dcomedi_8255.c37 unsigned long regbase; member
39 unsigned long regbase);
43 int dir, int port, int data, unsigned long regbase) in subdev_8255_io() argument
46 outb(data, dev->iobase + regbase + port); in subdev_8255_io()
49 return inb(dev->iobase + regbase + port); in subdev_8255_io()
53 int dir, int port, int data, unsigned long regbase) in subdev_8255_mmio() argument
56 writeb(data, dev->mmio + regbase + port); in subdev_8255_mmio()
59 return readb(dev->mmio + regbase + port); in subdev_8255_mmio()
68 unsigned long regbase = spriv->regbase; in subdev_8255_insn() local
76 s->state & 0xff, regbase); in subdev_8255_insn()
[all …]
D8255.h32 int data, unsigned long regbase),
33 unsigned long regbase);
37 int data, unsigned long regbase),
38 unsigned long regbase);
D8255.c108 unsigned long regbase = subdev_8255_regbase(s); in dev_8255_detach() local
110 release_region(regbase, I8255_SIZE); in dev_8255_detach()
/drivers/video/fbdev/core/
Dsvgalib.c23 void svga_wcrt_multi(void __iomem *regbase, const struct vga_regset *regset, u32 value) in svga_wcrt_multi() argument
28 regval = vga_rcrt(regbase, regset->regnum); in svga_wcrt_multi()
37 vga_wcrt(regbase, regset->regnum, regval); in svga_wcrt_multi()
43 void svga_wseq_multi(void __iomem *regbase, const struct vga_regset *regset, u32 value) in svga_wseq_multi() argument
48 regval = vga_rseq(regbase, regset->regnum); in svga_wseq_multi()
57 vga_wseq(regbase, regset->regnum, regval); in svga_wseq_multi()
78 void svga_set_default_gfx_regs(void __iomem *regbase) in svga_set_default_gfx_regs() argument
81 vga_wgfx(regbase, VGA_GFX_SR_VALUE, 0x00); in svga_set_default_gfx_regs()
82 vga_wgfx(regbase, VGA_GFX_SR_ENABLE, 0x00); in svga_set_default_gfx_regs()
83 vga_wgfx(regbase, VGA_GFX_COMPARE_VALUE, 0x00); in svga_set_default_gfx_regs()
[all …]
/drivers/rtc/
Drtc-sh.c97 void __iomem *regbase; member
114 tmp = readb(rtc->regbase + RCR1); in __sh_rtc_interrupt()
117 writeb(tmp, rtc->regbase + RCR1); in __sh_rtc_interrupt()
130 tmp = readb(rtc->regbase + RCR1); in __sh_rtc_alarm()
133 writeb(tmp, rtc->regbase + RCR1); in __sh_rtc_alarm()
145 tmp = readb(rtc->regbase + RCR2); in __sh_rtc_periodic()
148 writeb(tmp, rtc->regbase + RCR2); in __sh_rtc_periodic()
222 tmp = readb(rtc->regbase + RCR1); in sh_rtc_setaie()
229 writeb(tmp, rtc->regbase + RCR1); in sh_rtc_setaie()
239 tmp = readb(rtc->regbase + RCR1); in sh_rtc_proc()
[all …]
Drtc-vt8500.c73 void __iomem *regbase; member
88 isr = readl(vt8500_rtc->regbase + VT8500_RTC_IS); in vt8500_rtc_irq()
89 writel(isr, vt8500_rtc->regbase + VT8500_RTC_IS); in vt8500_rtc_irq()
106 date = readl(vt8500_rtc->regbase + VT8500_RTC_DR); in vt8500_rtc_read_time()
107 time = readl(vt8500_rtc->regbase + VT8500_RTC_TR); in vt8500_rtc_read_time()
129 vt8500_rtc->regbase + VT8500_RTC_DS); in vt8500_rtc_set_time()
134 vt8500_rtc->regbase + VT8500_RTC_TS); in vt8500_rtc_set_time()
144 alarm = readl(vt8500_rtc->regbase + VT8500_RTC_AS); in vt8500_rtc_read_alarm()
145 isr = readl(vt8500_rtc->regbase + VT8500_RTC_IS); in vt8500_rtc_read_alarm()
167 vt8500_rtc->regbase + VT8500_RTC_AS); in vt8500_rtc_set_alarm()
[all …]
/drivers/clocksource/
Dtimer-vt8500.c41 static void __iomem *regbase; variable
46 writel(3, regbase + TIMER_CTRL_VAL); in vt8500_timer_read()
47 while ((readl((regbase + TIMER_AS_VAL)) & TIMER_COUNT_R_ACTIVE) in vt8500_timer_read()
50 return readl(regbase + TIMER_COUNT_VAL); in vt8500_timer_read()
66 while ((readl(regbase + TIMER_AS_VAL) & TIMER_MATCH_W_ACTIVE) in vt8500_timer_set_next_event()
69 writel((unsigned long)alarm, regbase + TIMER_MATCH_VAL); in vt8500_timer_set_next_event()
74 writel(1, regbase + TIMER_IER_VAL); in vt8500_timer_set_next_event()
81 writel(readl(regbase + TIMER_CTRL_VAL) | 1, regbase + TIMER_CTRL_VAL); in vt8500_shutdown()
82 writel(0, regbase + TIMER_IER_VAL); in vt8500_shutdown()
98 writel(0xf, regbase + TIMER_STATUS_VAL); in vt8500_timer_interrupt()
[all …]
Dtimer-ti-dm-systimer.c367 u8 regbase; in dmtimer_systimer_setup() local
401 regbase = 0; in dmtimer_systimer_setup()
405 regbase = OMAP_TIMER_V2_FUNC_OFFSET; in dmtimer_systimer_setup()
406 t->pend = regbase + _OMAP_TIMER_WRITE_PEND_OFFSET; in dmtimer_systimer_setup()
410 t->load = regbase + _OMAP_TIMER_LOAD_OFFSET; in dmtimer_systimer_setup()
411 t->counter = regbase + _OMAP_TIMER_COUNTER_OFFSET; in dmtimer_systimer_setup()
412 t->ctrl = regbase + _OMAP_TIMER_CTRL_OFFSET; in dmtimer_systimer_setup()
413 t->wakeup = regbase + _OMAP_TIMER_WAKEUP_EN_OFFSET; in dmtimer_systimer_setup()
414 t->ifctrl = regbase + _OMAP_TIMER_IF_CTRL_OFFSET; in dmtimer_systimer_setup()
/drivers/gpio/
Dgpio-pxa.c66 void __iomem *regbase; member
165 return bank->regbase; in gpio_bank_base()
348 struct device_node *np, void __iomem *regbase) in pxa_init_gpio_chip() argument
376 bank->regbase = regbase + BANK_OFF(i); in pxa_init_gpio_chip()
389 grer = readl_relaxed(c->regbase + GRER_OFFSET) & ~c->irq_mask; in update_edge_detect()
390 gfer = readl_relaxed(c->regbase + GFER_OFFSET) & ~c->irq_mask; in update_edge_detect()
393 writel_relaxed(grer, c->regbase + GRER_OFFSET); in update_edge_detect()
394 writel_relaxed(gfer, c->regbase + GFER_OFFSET); in update_edge_detect()
417 gpdr = readl_relaxed(c->regbase + GPDR_OFFSET); in pxa_gpio_irq_type()
420 writel_relaxed(gpdr | mask, c->regbase + GPDR_OFFSET); in pxa_gpio_irq_type()
[all …]
Dgpio-f7188x.c71 unsigned int regbase; member
164 .regbase = _regbase, \
269 dir = superio_inb(sio->addr, gpio_dir(bank->regbase)); in f7188x_gpio_get_direction()
291 dir = superio_inb(sio->addr, gpio_dir(bank->regbase)); in f7188x_gpio_direction_in()
293 superio_outb(sio->addr, gpio_dir(bank->regbase), dir); in f7188x_gpio_direction_in()
312 dir = superio_inb(sio->addr, gpio_dir(bank->regbase)); in f7188x_gpio_get()
315 data = superio_inb(sio->addr, gpio_data_out(bank->regbase)); in f7188x_gpio_get()
317 data = superio_inb(sio->addr, gpio_data_in(bank->regbase)); in f7188x_gpio_get()
337 data_out = superio_inb(sio->addr, gpio_data_out(bank->regbase)); in f7188x_gpio_direction_out()
342 superio_outb(sio->addr, gpio_data_out(bank->regbase), data_out); in f7188x_gpio_direction_out()
[all …]
/drivers/spi/
Dspi-hisi-sfc-v3xx.c75 void __iomem *regbase; member
83 writel(0, host->regbase + HISI_SFC_V3XX_INT_MASK); in hisi_sfc_v3xx_disable_int()
88 writel(HISI_SFC_V3XX_INT_MASK_ALL, host->regbase + HISI_SFC_V3XX_INT_MASK); in hisi_sfc_v3xx_enable_int()
93 writel(HISI_SFC_V3XX_INT_MASK_ALL, host->regbase + HISI_SFC_V3XX_INT_CLR); in hisi_sfc_v3xx_clear_int()
105 reg = readl(host->regbase + HISI_SFC_V3XX_RAW_INT_STAT); in hisi_sfc_v3xx_handle_completion()
138 return readl_poll_timeout(host->regbase + HISI_SFC_V3XX_CMD_CFG, reg, in hisi_sfc_v3xx_wait_cmd_idle()
193 from = host->regbase + HISI_SFC_V3XX_CMD_DATABUF0; in hisi_sfc_v3xx_read_databuf()
230 to = host->regbase + HISI_SFC_V3XX_CMD_DATABUF0; in hisi_sfc_v3xx_write_databuf()
298 writel(op->addr.val, host->regbase + HISI_SFC_V3XX_CMD_ADDR); in hisi_sfc_v3xx_start_bus()
299 writel(op->cmd.opcode, host->regbase + HISI_SFC_V3XX_CMD_INS); in hisi_sfc_v3xx_start_bus()
[all …]
/drivers/mtd/spi-nor/controllers/
Dhisi-sfc.c93 void __iomem *regbase; member
107 return readl_poll_timeout(host->regbase + FMC_INT, reg, in hisi_spi_nor_wait_op_finish()
144 writel(reg, host->regbase + FMC_SPI_TIMING_CFG); in hisi_spi_nor_init()
187 writel(reg, host->regbase + FMC_CMD); in hisi_spi_nor_op_reg()
190 writel(reg, host->regbase + FMC_DATA_NUM); in hisi_spi_nor_op_reg()
193 writel(reg, host->regbase + FMC_OP_CFG); in hisi_spi_nor_op_reg()
195 writel(0xff, host->regbase + FMC_INT_CLR); in hisi_spi_nor_op_reg()
197 writel(reg, host->regbase + FMC_OP); in hisi_spi_nor_op_reg()
237 reg = readl(host->regbase + FMC_CFG); in hisi_spi_nor_dma_transfer()
242 writel(reg, host->regbase + FMC_CFG); in hisi_spi_nor_dma_transfer()
[all …]
/drivers/clk/uniphier/
Dclk-uniphier-cpugear.c21 unsigned int regbase; member
35 gear->regbase + UNIPHIER_CLK_CPUGEAR_SET, in uniphier_clk_cpugear_set_parent()
41 gear->regbase + UNIPHIER_CLK_CPUGEAR_UPD, in uniphier_clk_cpugear_set_parent()
48 gear->regbase + UNIPHIER_CLK_CPUGEAR_UPD, in uniphier_clk_cpugear_set_parent()
61 gear->regbase + UNIPHIER_CLK_CPUGEAR_STAT, &val); in uniphier_clk_cpugear_get_parent()
96 gear->regbase = data->regbase; in uniphier_clk_register_cpugear()
/drivers/scsi/ufs/
Dti-j721e-ufs.c22 void __iomem *regbase; in ti_j721e_ufs_probe() local
27 regbase = devm_platform_ioremap_resource(pdev, 0); in ti_j721e_ufs_probe()
28 if (IS_ERR(regbase)) in ti_j721e_ufs_probe()
29 return PTR_ERR(regbase); in ti_j721e_ufs_probe()
50 writel(reg, regbase + TI_UFS_SS_CTRL); in ti_j721e_ufs_probe()
/drivers/clk/at91/
Dsckc.c370 void __iomem *regbase = of_iomap(np, 0); in at91sam9x5_sckc_register() local
377 if (!regbase) in at91sam9x5_sckc_register()
380 slow_rc = at91_clk_register_slow_rc_osc(regbase, parent_names[0], in at91sam9x5_sckc_register()
404 slow_osc = at91_clk_register_slow_osc(regbase, parent_names[1], in at91sam9x5_sckc_register()
409 slowck = at91_clk_register_sam9x5_slow(regbase, "slowck", parent_names, in at91sam9x5_sckc_register()
463 void __iomem *regbase = of_iomap(np, 0); in of_sam9x60_sckc_setup() local
471 if (!regbase) in of_sam9x60_sckc_setup()
485 slow_osc = at91_clk_register_slow_osc(regbase, parent_names[1], in of_sam9x60_sckc_setup()
503 clk_data->hws[1] = at91_clk_register_sam9x5_slow(regbase, "td_slck", in of_sam9x60_sckc_setup()
572 void __iomem *regbase = of_iomap(np, 0); in of_sama5d4_sckc_setup() local
[all …]
/drivers/clk/socfpga/
Dclk-gate-s10.c68 struct clk *s10_register_gate(const struct stratix10_gate_clock *clks, void __iomem *regbase) in s10_register_gate() argument
79 socfpga_clk->hw.reg = regbase + clks->gate_reg; in s10_register_gate()
88 socfpga_clk->div_reg = regbase + clks->div_reg; in s10_register_gate()
96 socfpga_clk->bypass_reg = regbase + clks->bypass_reg; in s10_register_gate()
Dclk-periph-s10.c116 void __iomem *regbase) in s10_register_cnt_periph() argument
129 periph_clk->hw.reg = regbase + clks->offset; in s10_register_cnt_periph()
134 periph_clk->bypass_reg = regbase + clks->bypass_reg; in s10_register_cnt_periph()
/drivers/pinctrl/
Dpinctrl-at91.c41 void __iomem *regbase; /* PIO bank virtual address */ member
347 return gpio_chips[bank]->regbase; in pin_to_controller()
938 writel_relaxed(mask, at91_chip->regbase + PIO_PER); in at91_gpio_request_enable()
1415 void __iomem *pio = at91_gpio->regbase; in at91_gpio_get_direction()
1429 void __iomem *pio = at91_gpio->regbase; in at91_gpio_direction_input()
1439 void __iomem *pio = at91_gpio->regbase; in at91_gpio_get()
1451 void __iomem *pio = at91_gpio->regbase; in at91_gpio_set()
1461 void __iomem *pio = at91_gpio->regbase; in at91_gpio_set_multiple()
1476 void __iomem *pio = at91_gpio->regbase; in at91_gpio_direction_output()
1491 void __iomem *pio = at91_gpio->regbase; in at91_gpio_dbg_show()
[all …]
/drivers/iommu/
Domap-iommu.h56 void __iomem *regbase; member
258 return __raw_readl(obj->regbase + offs); in iommu_read_reg()
263 __raw_writel(val, obj->regbase + offs); in iommu_write_reg()
/drivers/gpu/drm/msm/edp/
Dedp.h49 void *msm_edp_aux_init(struct device *dev, void __iomem *regbase,
61 void *msm_edp_phy_init(struct device *dev, void __iomem *regbase);
Dedp_phy.c87 void *msm_edp_phy_init(struct device *dev, void __iomem *regbase) in msm_edp_phy_init() argument
95 phy->base = regbase; in msm_edp_phy_init()

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