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Searched refs:sclk (Results 1 – 25 of 113) sorted by relevance

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/drivers/clk/meson/
Dsclk-div.c31 static int sclk_div_maxval(struct meson_sclk_div_data *sclk) in sclk_div_maxval() argument
33 return (1 << sclk->div.width) - 1; in sclk_div_maxval()
36 static int sclk_div_maxdiv(struct meson_sclk_div_data *sclk) in sclk_div_maxdiv() argument
38 return sclk_div_maxval(sclk) + 1; in sclk_div_maxdiv()
51 struct meson_sclk_div_data *sclk) in sclk_div_bestdiv() argument
61 maxdiv = sclk_div_maxdiv(sclk); in sclk_div_bestdiv()
92 bestdiv = sclk_div_maxdiv(sclk); in sclk_div_bestdiv()
103 struct meson_sclk_div_data *sclk = meson_sclk_div_data(clk); in sclk_div_round_rate() local
106 div = sclk_div_bestdiv(hw, rate, prate, sclk); in sclk_div_round_rate()
112 struct meson_sclk_div_data *sclk) in sclk_apply_ratio() argument
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/drivers/clk/hisilicon/
Dclkgate-separated.c34 struct clkgate_separated *sclk; in clkgate_separated_enable() local
38 sclk = container_of(hw, struct clkgate_separated, hw); in clkgate_separated_enable()
39 if (sclk->lock) in clkgate_separated_enable()
40 spin_lock_irqsave(sclk->lock, flags); in clkgate_separated_enable()
41 reg = BIT(sclk->bit_idx); in clkgate_separated_enable()
42 writel_relaxed(reg, sclk->enable); in clkgate_separated_enable()
43 readl_relaxed(sclk->enable + CLKGATE_SEPERATED_STATUS); in clkgate_separated_enable()
44 if (sclk->lock) in clkgate_separated_enable()
45 spin_unlock_irqrestore(sclk->lock, flags); in clkgate_separated_enable()
51 struct clkgate_separated *sclk; in clkgate_separated_disable() local
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/drivers/clk/
Dclk-u300.c455 static void syscon_block_reset_enable(struct clk_syscon *sclk) in syscon_block_reset_enable() argument
461 if (!sclk->res_reg) in syscon_block_reset_enable()
464 val = readw(sclk->res_reg); in syscon_block_reset_enable()
465 val |= BIT(sclk->res_bit); in syscon_block_reset_enable()
466 writew(val, sclk->res_reg); in syscon_block_reset_enable()
468 sclk->reset = true; in syscon_block_reset_enable()
471 static void syscon_block_reset_disable(struct clk_syscon *sclk) in syscon_block_reset_disable() argument
477 if (!sclk->res_reg) in syscon_block_reset_disable()
480 val = readw(sclk->res_reg); in syscon_block_reset_disable()
481 val &= ~BIT(sclk->res_bit); in syscon_block_reset_disable()
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Dclk-scmi.c105 static int scmi_clk_ops_init(struct device *dev, struct scmi_clk *sclk) in scmi_clk_ops_init() argument
114 .name = sclk->info->name, in scmi_clk_ops_init()
117 sclk->hw.init = &init; in scmi_clk_ops_init()
118 ret = devm_clk_hw_register(dev, &sclk->hw); in scmi_clk_ops_init()
122 if (sclk->info->rate_discrete) { in scmi_clk_ops_init()
123 int num_rates = sclk->info->list.num_rates; in scmi_clk_ops_init()
128 min_rate = sclk->info->list.rates[0]; in scmi_clk_ops_init()
129 max_rate = sclk->info->list.rates[num_rates - 1]; in scmi_clk_ops_init()
131 min_rate = sclk->info->range.min_rate; in scmi_clk_ops_init()
132 max_rate = sclk->info->range.max_rate; in scmi_clk_ops_init()
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Dclk-scpi.c140 struct scpi_clk *sclk, const char *name) in scpi_clk_ops_init() argument
150 sclk->hw.init = &init; in scpi_clk_ops_init()
151 sclk->scpi_ops = get_scpi_ops(); in scpi_clk_ops_init()
154 sclk->info = sclk->scpi_ops->dvfs_get_info(sclk->id); in scpi_clk_ops_init()
155 if (IS_ERR(sclk->info)) in scpi_clk_ops_init()
156 return PTR_ERR(sclk->info); in scpi_clk_ops_init()
158 if (sclk->scpi_ops->clk_get_range(sclk->id, &min, &max) || !max) in scpi_clk_ops_init()
164 ret = devm_clk_hw_register(dev, &sclk->hw); in scpi_clk_ops_init()
166 clk_hw_set_rate_range(&sclk->hw, min, max); in scpi_clk_ops_init()
178 struct scpi_clk *sclk; in scpi_of_clk_src_get() local
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Dclk-nomadik.c302 struct clk_src *sclk = to_src(hw); in src_clk_enable() local
303 u32 enreg = sclk->group1 ? SRC_PCKEN1 : SRC_PCKEN0; in src_clk_enable()
304 u32 sreg = sclk->group1 ? SRC_PCKSR1 : SRC_PCKSR0; in src_clk_enable()
306 writel(sclk->clkbit, src_base + enreg); in src_clk_enable()
308 while (!(readl(src_base + sreg) & sclk->clkbit)) in src_clk_enable()
315 struct clk_src *sclk = to_src(hw); in src_clk_disable() local
316 u32 disreg = sclk->group1 ? SRC_PCKDIS1 : SRC_PCKDIS0; in src_clk_disable()
317 u32 sreg = sclk->group1 ? SRC_PCKSR1 : SRC_PCKSR0; in src_clk_disable()
319 writel(sclk->clkbit, src_base + disreg); in src_clk_disable()
321 while (readl(src_base + sreg) & sclk->clkbit) in src_clk_disable()
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/drivers/clk/microchip/
Dclk-core.c774 struct pic32_sys_clk *sclk = clkhw_to_sys_clk(hw); in sclk_get_rate() local
777 div = (readl(sclk->slew_reg) >> SLEW_SYSDIV_SHIFT) & SLEW_SYSDIV; in sclk_get_rate()
792 struct pic32_sys_clk *sclk = clkhw_to_sys_clk(hw); in sclk_set_rate() local
799 spin_lock_irqsave(&sclk->core->reg_lock, flags); in sclk_set_rate()
802 v = readl(sclk->slew_reg); in sclk_set_rate()
808 writel(v, sclk->slew_reg); in sclk_set_rate()
811 err = readl_poll_timeout_atomic(sclk->slew_reg, v, in sclk_set_rate()
814 spin_unlock_irqrestore(&sclk->core->reg_lock, flags); in sclk_set_rate()
821 struct pic32_sys_clk *sclk = clkhw_to_sys_clk(hw); in sclk_get_parent() local
824 v = (readl(sclk->mux_reg) >> OSC_CUR_SHIFT) & OSC_CUR_MASK; in sclk_get_parent()
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/drivers/gpu/drm/nouveau/nvkm/subdev/clk/
Dgk104.c68 u32 sclk; in read_pll() local
77 sclk = device->crystal; in read_pll()
81 sclk = read_pll(clk, 0x132020); in read_pll()
85 sclk = read_div(clk, 0, 0x137320, 0x137330); in read_pll()
92 sclk = read_div(clk, (pll & 0xff) / 0x20, 0x137120, 0x137140); in read_pll()
101 sclk = (sclk * N) + (((u16)(fN + 4096) * sclk) >> 13); in read_pll()
102 return sclk / (M * P); in read_pll()
121 u32 sclk = read_vco(clk, dsrc + (doff * 4)); in read_div() local
123 return (sclk * 2) / sdiv; in read_div()
149 u32 sclk, sdiv; in read_clk() local
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Dgf100.c67 u32 sclk; in read_pll() local
75 sclk = device->crystal; in read_pll()
79 sclk = nvkm_clk_read(&clk->base, nv_clk_src_mpllsrc); in read_pll()
82 sclk = nvkm_clk_read(&clk->base, nv_clk_src_mpllsrcref); in read_pll()
88 sclk = read_div(clk, (pll & 0xff) / 0x20, 0x137120, 0x137140); in read_pll()
94 return sclk * N / M / P; in read_pll()
102 u32 sclk, sctl, sdiv = 2; in read_div() local
112 sclk = read_vco(clk, dsrc + (doff * 4)); in read_div()
126 return (sclk * 2) / sdiv; in read_div()
138 u32 sclk, sdiv; in read_clk() local
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Dgt215.c64 u32 sctl, sdiv, sclk; in read_clk() local
99 sclk = read_vco(clk, idx); in read_clk()
101 return (sclk * 2) / sdiv; in read_clk()
112 u32 sclk = 0, P = 1, N = 1, M = 1; in read_pll() local
128 sclk = read_clk(clk, 0x00 + idx, false); in read_pll()
131 sclk = read_clk(clk, 0x10 + idx, false); in read_pll()
139 return sclk * N / MP; in read_pll()
191 u32 oclk, sclk, sdiv; in gt215_clk_info() local
207 sclk = read_vco(clk, idx); in gt215_clk_info()
208 sdiv = min((sclk * 2) / khz, (u32)65); in gt215_clk_info()
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/drivers/gpu/drm/radeon/
Drv730_dpm.c41 RV770_SMC_SCLK_VALUE *sclk) in rv730_populate_sclk_value() argument
108 sclk->sclk_value = cpu_to_be32(engine_clock); in rv730_populate_sclk_value()
109 sclk->vCG_SPLL_FUNC_CNTL = cpu_to_be32(spll_func_cntl); in rv730_populate_sclk_value()
110 sclk->vCG_SPLL_FUNC_CNTL_2 = cpu_to_be32(spll_func_cntl_2); in rv730_populate_sclk_value()
111 sclk->vCG_SPLL_FUNC_CNTL_3 = cpu_to_be32(spll_func_cntl_3); in rv730_populate_sclk_value()
112 sclk->vCG_SPLL_SPREAD_SPECTRUM = cpu_to_be32(cg_spll_spread_spectrum); in rv730_populate_sclk_value()
113 sclk->vCG_SPLL_SPREAD_SPECTRUM_2 = cpu_to_be32(cg_spll_spread_spectrum_2); in rv730_populate_sclk_value()
304 table->ACPIState.levels[0].sclk.vCG_SPLL_FUNC_CNTL = cpu_to_be32(spll_func_cntl); in rv730_populate_smc_acpi_state()
305 table->ACPIState.levels[0].sclk.vCG_SPLL_FUNC_CNTL_2 = cpu_to_be32(spll_func_cntl_2); in rv730_populate_smc_acpi_state()
306 table->ACPIState.levels[0].sclk.vCG_SPLL_FUNC_CNTL_3 = cpu_to_be32(spll_func_cntl_3); in rv730_populate_smc_acpi_state()
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Dbtc_dpm.c1244 u32 *sclk, u32 *mclk) in btc_skip_blacklist_clocks() argument
1248 if ((sclk == NULL) || (mclk == NULL)) in btc_skip_blacklist_clocks()
1254 if ((btc_blacklist_clocks[i].sclk == *sclk) && in btc_skip_blacklist_clocks()
1261 *sclk = btc_get_valid_sclk(rdev, max_sclk, *sclk + 1); in btc_skip_blacklist_clocks()
1263 if (*sclk < max_sclk) in btc_skip_blacklist_clocks()
1264 btc_skip_blacklist_clocks(rdev, max_sclk, max_mclk, sclk, mclk); in btc_skip_blacklist_clocks()
1274 if ((pl->mclk == 0) || (pl->sclk == 0)) in btc_adjust_clock_combinations()
1277 if (pl->mclk == pl->sclk) in btc_adjust_clock_combinations()
1280 if (pl->mclk > pl->sclk) { in btc_adjust_clock_combinations()
1281 if (((pl->mclk + (pl->sclk - 1)) / pl->sclk) > rdev->pm.dpm.dyn_state.mclk_sclk_ratio) in btc_adjust_clock_combinations()
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Drv770_dpm.c271 a_n = (int)state->medium.sclk * pi->lmp + in rv770_populate_smc_t()
272 (int)state->low.sclk * (R600_AH_DFLT - pi->rlp); in rv770_populate_smc_t()
273 a_d = (int)state->low.sclk * (100 - (int)pi->rlp) + in rv770_populate_smc_t()
274 (int)state->medium.sclk * pi->lmp; in rv770_populate_smc_t()
279 a_n = (int)state->high.sclk * pi->lhp + (int)state->medium.sclk * in rv770_populate_smc_t()
281 a_d = (int)state->medium.sclk * (100 - (int)pi->rmp) + in rv770_populate_smc_t()
282 (int)state->high.sclk * pi->lhp; in rv770_populate_smc_t()
485 RV770_SMC_SCLK_VALUE *sclk) in rv770_populate_sclk_value() argument
555 sclk->sclk_value = cpu_to_be32(engine_clock); in rv770_populate_sclk_value()
556 sclk->vCG_SPLL_FUNC_CNTL = cpu_to_be32(spll_func_cntl); in rv770_populate_sclk_value()
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Dtrinity_dpm.c584 u32 index, u32 sclk) in trinity_set_divider_value() argument
592 sclk, false, &dividers); in trinity_set_divider_value()
602 sclk/2, false, &dividers); in trinity_set_divider_value()
722 trinity_set_divider_value(rdev, index, pl->sclk); in trinity_program_power_level()
969 if (new_ps->levels[new_ps->num_levels - 1].sclk >= in trinity_set_uvd_clock_before_set_eng_clock()
970 current_ps->levels[current_ps->num_levels - 1].sclk) in trinity_set_uvd_clock_before_set_eng_clock()
983 if (new_ps->levels[new_ps->num_levels - 1].sclk < in trinity_set_uvd_clock_after_set_eng_clock()
984 current_ps->levels[current_ps->num_levels - 1].sclk) in trinity_set_uvd_clock_after_set_eng_clock()
1334 static u8 trinity_calculate_vce_wm(struct radeon_device *rdev, u32 sclk) in trinity_calculate_vce_wm() argument
1336 if (sclk < 20000) in trinity_calculate_vce_wm()
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Drv740_dpm.c121 RV770_SMC_SCLK_VALUE *sclk) in rv740_populate_sclk_value() argument
176 sclk->sclk_value = cpu_to_be32(engine_clock); in rv740_populate_sclk_value()
177 sclk->vCG_SPLL_FUNC_CNTL = cpu_to_be32(spll_func_cntl); in rv740_populate_sclk_value()
178 sclk->vCG_SPLL_FUNC_CNTL_2 = cpu_to_be32(spll_func_cntl_2); in rv740_populate_sclk_value()
179 sclk->vCG_SPLL_FUNC_CNTL_3 = cpu_to_be32(spll_func_cntl_3); in rv740_populate_sclk_value()
180 sclk->vCG_SPLL_SPREAD_SPECTRUM = cpu_to_be32(cg_spll_spread_spectrum); in rv740_populate_sclk_value()
181 sclk->vCG_SPLL_SPREAD_SPECTRUM_2 = cpu_to_be32(cg_spll_spread_spectrum_2); in rv740_populate_sclk_value()
386 table->ACPIState.levels[0].sclk.vCG_SPLL_FUNC_CNTL = cpu_to_be32(spll_func_cntl); in rv740_populate_smc_acpi_state()
387 table->ACPIState.levels[0].sclk.vCG_SPLL_FUNC_CNTL_2 = cpu_to_be32(spll_func_cntl_2); in rv740_populate_smc_acpi_state()
388 table->ACPIState.levels[0].sclk.vCG_SPLL_FUNC_CNTL_3 = cpu_to_be32(spll_func_cntl_3); in rv740_populate_smc_acpi_state()
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Dni_dpm.c811 if (ps->performance_levels[i].sclk > max_limits->sclk) in ni_apply_state_adjust_rules()
812 ps->performance_levels[i].sclk = max_limits->sclk; in ni_apply_state_adjust_rules()
830 btc_skip_blacklist_clocks(rdev, max_limits->sclk, max_limits->mclk, in ni_apply_state_adjust_rules()
831 &ps->performance_levels[0].sclk, in ni_apply_state_adjust_rules()
835 if (ps->performance_levels[i].sclk < ps->performance_levels[i - 1].sclk) in ni_apply_state_adjust_rules()
836 ps->performance_levels[i].sclk = ps->performance_levels[i - 1].sclk; in ni_apply_state_adjust_rules()
865 btc_skip_blacklist_clocks(rdev, max_limits->sclk, max_limits->mclk, in ni_apply_state_adjust_rules()
866 &ps->performance_levels[i].sclk, in ni_apply_state_adjust_rules()
875 ps->performance_levels[i].sclk, in ni_apply_state_adjust_rules()
1622 (u8)rv770_calculate_memory_refresh_rate(rdev, pl->sclk); in ni_populate_memory_timing_parameters()
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Dkv_dpm.c535 u32 index, u32 sclk) in kv_set_divider_value() argument
542 sclk, false, &dividers); in kv_set_divider_value()
547 pi->graphics_level[index].SclkFrequency = cpu_to_be32(sclk); in kv_set_divider_value()
724 if (table->entries[i].clk == pi->boot_pl.sclk) in kv_program_bootup_state()
738 if (table->entries[i].sclk_frequency == pi->boot_pl.sclk) in kv_program_bootup_state()
1717 if ((table->entries[i].clk >= new_ps->levels[0].sclk) || in kv_set_valid_clock_range()
1725 if (table->entries[i].clk <= new_ps->levels[new_ps->num_levels - 1].sclk) in kv_set_valid_clock_range()
1731 if ((new_ps->levels[0].sclk - table->entries[pi->highest_valid].clk) > in kv_set_valid_clock_range()
1732 (table->entries[pi->lowest_valid].clk - new_ps->levels[new_ps->num_levels - 1].sclk)) in kv_set_valid_clock_range()
1742 if (table->entries[i].sclk_frequency >= new_ps->levels[0].sclk || in kv_set_valid_clock_range()
[all …]
Dsumo_dpm.c347 u32 highest_engine_clock = ps->levels[ps->num_levels - 1].sclk; in sumo_program_bsp()
350 highest_engine_clock = pi->boost_pl.sclk; in sumo_program_bsp()
411 m_a = asi * ps->levels[i].sclk / 100; in sumo_program_at()
421 m_a = asi * pi->boost_pl.sclk / 100; in sumo_program_at()
555 pl->sclk, false, &dividers); in sumo_program_power_level()
671 pi->boost_pl.sclk = pi->sys_info.boost_sclk; in sumo_patch_boost_state()
790 pi->acpi_pl.sclk, in sumo_program_acpi_power_level()
844 if (new_ps->levels[new_ps->num_levels - 1].sclk >= in sumo_set_uvd_clock_before_set_eng_clock()
845 current_ps->levels[current_ps->num_levels - 1].sclk) in sumo_set_uvd_clock_before_set_eng_clock()
862 if (new_ps->levels[new_ps->num_levels - 1].sclk < in sumo_set_uvd_clock_after_set_eng_clock()
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/drivers/tty/serial/8250/
D8250_em.c24 struct clk *sclk; member
100 priv->sclk = devm_clk_get(&pdev->dev, "sclk"); in serial8250_em_probe()
101 if (IS_ERR(priv->sclk)) { in serial8250_em_probe()
103 return PTR_ERR(priv->sclk); in serial8250_em_probe()
114 clk_prepare_enable(priv->sclk); in serial8250_em_probe()
115 up.port.uartclk = clk_get_rate(priv->sclk); in serial8250_em_probe()
126 clk_disable_unprepare(priv->sclk); in serial8250_em_probe()
140 clk_disable_unprepare(priv->sclk); in serial8250_em_remove()
/drivers/power/reset/
Dat91-reset.c56 struct clk *sclk; member
220 reset->sclk = devm_clk_get(&pdev->dev, NULL); in at91_reset_probe()
221 if (IS_ERR(reset->sclk)) in at91_reset_probe()
222 return PTR_ERR(reset->sclk); in at91_reset_probe()
224 ret = clk_prepare_enable(reset->sclk); in at91_reset_probe()
241 clk_disable_unprepare(reset->sclk); in at91_reset_probe()
255 clk_disable_unprepare(reset->sclk); in at91_reset_remove()
Dat91-poweroff.c55 struct clk *sclk; member
164 at91_shdwc.sclk = devm_clk_get(&pdev->dev, NULL); in at91_poweroff_probe()
165 if (IS_ERR(at91_shdwc.sclk)) in at91_poweroff_probe()
166 return PTR_ERR(at91_shdwc.sclk); in at91_poweroff_probe()
168 ret = clk_prepare_enable(at91_shdwc.sclk); in at91_poweroff_probe()
203 clk_disable_unprepare(at91_shdwc.sclk); in at91_poweroff_probe()
215 clk_disable_unprepare(at91_shdwc.sclk); in at91_poweroff_remove()
/drivers/media/dvb-frontends/
Dcx24110.c544 s32 afc; unsigned sclk; in cx24110_get_frontend() local
548 sclk = cx24110_readreg (state, 0x07) & 0x03; in cx24110_get_frontend()
551 if (sclk==0) sclk=90999000L/2L; in cx24110_get_frontend()
552 else if (sclk==1) sclk=60666000L; in cx24110_get_frontend()
553 else if (sclk==2) sclk=80888000L; in cx24110_get_frontend()
554 else sclk=90999000L; in cx24110_get_frontend()
555 sclk>>=8; in cx24110_get_frontend()
556 afc = sclk*(cx24110_readreg (state, 0x44)&0x1f)+ in cx24110_get_frontend()
557 ((sclk*cx24110_readreg (state, 0x45))>>8)+ in cx24110_get_frontend()
558 ((sclk*cx24110_readreg (state, 0x46))>>16); in cx24110_get_frontend()
/drivers/clocksource/
Dtimer-atmel-st.c185 struct clk *sclk; in atmel_st_timer_init() local
216 sclk = of_clk_get(node, 0); in atmel_st_timer_init()
217 if (IS_ERR(sclk)) { in atmel_st_timer_init()
219 return PTR_ERR(sclk); in atmel_st_timer_init()
222 ret = clk_prepare_enable(sclk); in atmel_st_timer_init()
228 sclk_rate = clk_get_rate(sclk); in atmel_st_timer_init()
/drivers/gpu/drm/amd/pm/powerplay/
Dkv_dpm.c662 u32 index, u32 sclk) in kv_set_divider_value() argument
669 sclk, false, &dividers); in kv_set_divider_value()
674 pi->graphics_level[index].SclkFrequency = cpu_to_be32(sclk); in kv_set_divider_value()
807 if (table->entries[i].clk == pi->boot_pl.sclk) in kv_program_bootup_state()
821 if (table->entries[i].sclk_frequency == pi->boot_pl.sclk) in kv_program_bootup_state()
1770 if ((table->entries[i].clk >= new_ps->levels[0].sclk) || in kv_set_valid_clock_range()
1778 if (table->entries[i].clk <= new_ps->levels[new_ps->num_levels - 1].sclk) in kv_set_valid_clock_range()
1784 if ((new_ps->levels[0].sclk - table->entries[pi->highest_valid].clk) > in kv_set_valid_clock_range()
1785 (table->entries[pi->lowest_valid].clk - new_ps->levels[new_ps->num_levels - 1].sclk)) in kv_set_valid_clock_range()
1795 if (table->entries[i].sclk_frequency >= new_ps->levels[0].sclk || in kv_set_valid_clock_range()
[all …]
Dsi_dpm.c1831 SISLANDS_SMC_SCLK_VALUE *sclk);
2402 prev_sclk = state->performance_levels[i-1].sclk; in si_populate_power_containment_values()
2403 max_sclk = state->performance_levels[i].sclk; in si_populate_power_containment_values()
2421 if (min_sclk < state->performance_levels[0].sclk) in si_populate_power_containment_values()
2422 min_sclk = state->performance_levels[0].sclk; in si_populate_power_containment_values()
2496 if ((state->performance_levels[i].sclk >= adev->pm.dpm.sq_ramping_threshold) && in si_populate_sq_ramping_values()
2934 u32 sclk = 0; in si_init_smc_spll_table() local
2947 ret = si_calculate_sclk_params(adev, sclk, &sclk_params); in si_init_smc_spll_table()
2979 sclk += 512; in si_init_smc_spll_table()
3163 if (new_state->performance_levels[new_state->performance_level_count - 1].sclk >= in ni_set_uvd_clock_before_set_eng_clock()
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