| /drivers/gpu/drm/amd/amdgpu/ |
| D | mmhub_v1_0.c | 713 uint32_t sec_cnt, ded_cnt; in mmhub_v1_0_get_ras_error_count() local
719 sec_cnt = (value & in mmhub_v1_0_get_ras_error_count()
722 if (sec_cnt) { in mmhub_v1_0_get_ras_error_count()
726 sec_cnt); in mmhub_v1_0_get_ras_error_count()
727 *sec_count += sec_cnt; in mmhub_v1_0_get_ras_error_count()
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| D | gfx_v9_4.c | 834 uint32_t sec_cnt, ded_cnt; in gfx_v9_4_ras_error_count() local
842 sec_cnt = (value & gfx_v9_4_ras_fields[i].sec_count_mask) >> in gfx_v9_4_ras_error_count()
844 if (sec_cnt) { in gfx_v9_4_ras_error_count()
848 sec_cnt); in gfx_v9_4_ras_error_count()
849 *sec_count += sec_cnt; in gfx_v9_4_ras_error_count()
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| D | mmhub_v9_4.c | 1563 uint32_t sec_cnt, ded_cnt; in mmhub_v9_4_get_ras_error_count() local
1569 sec_cnt = (value & in mmhub_v9_4_get_ras_error_count()
1572 if (sec_cnt) { in mmhub_v9_4_get_ras_error_count()
1575 sec_cnt); in mmhub_v9_4_get_ras_error_count()
1576 *sec_count += sec_cnt; in mmhub_v9_4_get_ras_error_count()
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| D | sdma_v4_0.c | 2592 uint32_t sec_cnt; in sdma_v4_0_get_ras_error_count() local
2599 sec_cnt = (value & in sdma_v4_0_get_ras_error_count()
2602 if (sec_cnt) { in sdma_v4_0_get_ras_error_count()
2605 instance, sec_cnt); in sdma_v4_0_get_ras_error_count()
2606 *sec_count += sec_cnt; in sdma_v4_0_get_ras_error_count()
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| D | gfx_v9_0.c | 6566 uint32_t sec_cnt, ded_cnt; in gfx_v9_0_ras_error_count() local
6574 sec_cnt = (value & in gfx_v9_0_ras_error_count()
6577 if (sec_cnt) { in gfx_v9_0_ras_error_count()
6582 sec_cnt); in gfx_v9_0_ras_error_count()
6583 *sec_count += sec_cnt; in gfx_v9_0_ras_error_count()
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| /drivers/staging/rts5208/ |
| D | rtsx_scsi.c | 841 u16 sec_cnt; in read_write() local
886 sec_cnt = ((u16)(srb->cmnd[7]) << 8) | srb->cmnd[8]; in read_write()
890 sec_cnt = srb->cmnd[4]; in read_write()
891 if (sec_cnt == 0) in read_write()
892 sec_cnt = 256; in read_write()
899 sec_cnt = ((u16)(srb->cmnd[9]) << 8) | srb->cmnd[10]; in read_write()
910 ((start_sec + sec_cnt) > get_card_size(chip, lun))) { in read_write()
915 if (sec_cnt == 0) { in read_write()
940 retval = card_rw(srb, chip, start_sec, sec_cnt); in read_write()
2686 u16 sec_cnt; in led_shine() local
[all …]
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| D | ms.c | 96 u8 tpc, u16 sec_cnt, u8 cfg, bool mode_2k, in ms_transfer_data() argument
120 MS_SECTOR_CNT_H, 0xFF, (u8)(sec_cnt >> 8)); in ms_transfer_data()
121 rtsx_add_cmd(chip, WRITE_REG_CMD, MS_SECTOR_CNT_L, 0xFF, (u8)sec_cnt); in ms_transfer_data()
131 trans_dma_enable(dir, chip, sec_cnt * 512, DMA_512); in ms_transfer_data()
2543 u32 start_sec, u16 sec_cnt, u8 cmd) argument
2549 data[1] = (u8)(sec_cnt >> 8);
2550 data[2] = (u8)sec_cnt;
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| D | rtsx_card.c | 939 u32 sec_addr, u16 sec_cnt) in card_rw() argument
951 retval = chip->rw_card[lun](srb, chip, sec_addr, sec_cnt); in card_rw()
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| D | rtsx_card.h | 1002 u32 sec_addr, u16 sec_cnt);
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| D | rtsx_chip.h | 341 u32 sec_addr, u16 sec_cnt);
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| /drivers/memstick/host/ |
| D | rtsx_pci_ms.c | 134 u16 sec_cnt = (u16)(length / 512); in ms_transfer_data() local
156 0xFF, (u8)(sec_cnt >> 8)); in ms_transfer_data()
158 0xFF, (u8)sec_cnt); in ms_transfer_data()
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| D | rtsx_usb_ms.c | 236 u16 sec_cnt = (u16)(length / 512); in ms_transfer_data() local
268 0xFF, (u8)(sec_cnt >> 8)); in ms_transfer_data()
270 0xFF, (u8)sec_cnt); in ms_transfer_data()
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| /drivers/mtd/nand/raw/ |
| D | cadence-nand-controller.c | 1210 u32 sec_size = 0, offset = 0, sec_cnt = 1; in cadence_nand_prepare_data_size() local
1220 sec_cnt = cdns_chip->sector_count; in cadence_nand_prepare_data_size()
1225 sec_cnt = cdns_chip->sector_count; in cadence_nand_prepare_data_size()
1241 reg |= FIELD_PREP(TRAN_CFG_0_SEC_CNT, sec_cnt); in cadence_nand_prepare_data_size()
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