| /drivers/gpu/drm/radeon/ |
| D | radeon_clocks.c | 42 struct radeon_pll *spll = &rdev->clock.spll; in radeon_legacy_get_engine_clock() local
48 fb_div *= spll->reference_freq; in radeon_legacy_get_engine_clock()
111 struct radeon_pll *spll = &rdev->clock.spll; in radeon_read_clocks_OF() local
150 spll->reference_freq = mpll->reference_freq = p1pll->reference_freq; in radeon_read_clocks_OF()
151 spll->reference_div = mpll->reference_div = in radeon_read_clocks_OF()
186 struct radeon_pll *spll = &rdev->clock.spll; in radeon_get_clock_info() local
214 if (spll->reference_div < 2) in radeon_get_clock_info()
215 spll->reference_div = in radeon_get_clock_info()
220 mpll->reference_div = spll->reference_div; in radeon_get_clock_info()
233 spll->reference_freq = 1432; in radeon_get_clock_info()
[all …]
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| D | radeon_combios.c | 739 struct radeon_pll *spll = &rdev->clock.spll; in radeon_combios_get_clock_info() local
766 spll->reference_freq = RBIOS16(pll_info + 0x1a); in radeon_combios_get_clock_info()
767 spll->reference_div = RBIOS16(pll_info + 0x1c); in radeon_combios_get_clock_info()
768 spll->pll_out_min = RBIOS32(pll_info + 0x1e); in radeon_combios_get_clock_info()
769 spll->pll_out_max = RBIOS32(pll_info + 0x22); in radeon_combios_get_clock_info()
772 spll->pll_in_min = RBIOS32(pll_info + 0x48); in radeon_combios_get_clock_info()
773 spll->pll_in_max = RBIOS32(pll_info + 0x4c); in radeon_combios_get_clock_info()
776 spll->pll_in_min = 40; in radeon_combios_get_clock_info()
777 spll->pll_in_max = 500; in radeon_combios_get_clock_info()
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| D | radeon_atombios.c | 1138 struct radeon_pll *spll = &rdev->clock.spll; in radeon_atom_get_clock_info() local
1191 spll->reference_freq = in radeon_atom_get_clock_info()
1194 spll->reference_freq = in radeon_atom_get_clock_info()
1196 spll->reference_div = 0; in radeon_atom_get_clock_info()
1198 spll->pll_out_min = in radeon_atom_get_clock_info()
1200 spll->pll_out_max = in radeon_atom_get_clock_info()
1204 if (spll->pll_out_min == 0) { in radeon_atom_get_clock_info()
1206 spll->pll_out_min = 64800; in radeon_atom_get_clock_info()
1208 spll->pll_out_min = 20000; in radeon_atom_get_clock_info()
1211 spll->pll_in_min = in radeon_atom_get_clock_info()
[all …]
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| D | rv6xx_dpm.c | 163 u32 ref_clk = rdev->clock.spll.reference_freq; in rv6xx_output_stepping()
428 u32 ref_clk = rdev->clock.spll.reference_freq; in rv6xx_compute_count_for_delay()
551 u32 ref_clk = rdev->clock.spll.reference_freq; in rv6xx_program_engine_spread_spectrum()
840 u32 ref_clk = rdev->clock.spll.reference_freq; in rv6xx_program_bsp()
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| D | rv740_dpm.c | 131 u32 reference_clock = rdev->clock.spll.reference_freq; in rv740_populate_sclk_value()
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| D | rs780_dpm.c | 992 u32 sclk = (rdev->clock.spll.reference_freq * current_fb_div) / in rs780_dpm_debugfs_print_current_performance_level()
1014 u32 sclk = (rdev->clock.spll.reference_freq * current_fb_div) / in rs780_dpm_get_current_sclk()
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| D | rv730_dpm.c | 51 u32 reference_clock = rdev->clock.spll.reference_freq; in rv730_populate_sclk_value()
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| D | radeon_kms.c | 340 *value = rdev->clock.spll.reference_freq * 10; in radeon_info_ioctl()
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| D | radeon_uvd.c | 969 unsigned vco_freq, ref_freq = rdev->clock.spll.reference_freq; in radeon_uvd_calc_upll_dividers()
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| D | rv770.c | 796 u32 reference_clock = rdev->clock.spll.reference_freq; in rv770_get_xclk()
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| /drivers/gpu/drm/amd/amdgpu/ |
| D | amdgpu_atomfirmware.c | 380 struct amdgpu_pll *spll = &adev->clock.spll; in amdgpu_atomfirmware_get_clock_info() local
418 spll->reference_freq = le32_to_cpu(smu_info->v31.core_refclk_10khz); in amdgpu_atomfirmware_get_clock_info()
420 spll->reference_div = 0; in amdgpu_atomfirmware_get_clock_info()
421 spll->min_post_div = 1; in amdgpu_atomfirmware_get_clock_info()
422 spll->max_post_div = 1; in amdgpu_atomfirmware_get_clock_info()
423 spll->min_ref_div = 2; in amdgpu_atomfirmware_get_clock_info()
424 spll->max_ref_div = 0xff; in amdgpu_atomfirmware_get_clock_info()
425 spll->min_feedback_div = 4; in amdgpu_atomfirmware_get_clock_info()
426 spll->max_feedback_div = 0xff; in amdgpu_atomfirmware_get_clock_info()
427 spll->best_vco = 0; in amdgpu_atomfirmware_get_clock_info()
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| D | amdgpu_atombios.c | 570 struct amdgpu_pll *spll = &adev->clock.spll; in amdgpu_atombios_get_clock_info() local
616 spll->reference_freq = in amdgpu_atombios_get_clock_info()
618 spll->reference_div = 0; in amdgpu_atombios_get_clock_info()
620 spll->pll_out_min = in amdgpu_atombios_get_clock_info()
622 spll->pll_out_max = in amdgpu_atombios_get_clock_info()
626 if (spll->pll_out_min == 0) in amdgpu_atombios_get_clock_info()
627 spll->pll_out_min = 64800; in amdgpu_atombios_get_clock_info()
629 spll->pll_in_min = in amdgpu_atombios_get_clock_info()
631 spll->pll_in_max = in amdgpu_atombios_get_clock_info()
634 spll->min_post_div = 1; in amdgpu_atombios_get_clock_info()
[all …]
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| D | si.c | 1353 u32 reference_clock = adev->clock.spll.reference_freq; in si_get_xclk()
1607 unsigned vco_freq, ref_freq = adev->clock.spll.reference_freq; in si_calc_upll_dividers()
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| D | nv.c | 143 return adev->clock.spll.reference_freq; in nv_get_xclk()
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| D | amdgpu.h | 355 struct amdgpu_pll spll; member
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| D | cik.c | 843 u32 reference_clock = adev->clock.spll.reference_freq; in cik_get_xclk()
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| D | vi.c | 329 u32 reference_clock = adev->clock.spll.reference_freq; in vi_get_xclk()
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| D | soc15.c | 247 u32 reference_clock = adev->clock.spll.reference_freq; in soc15_get_xclk()
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| /drivers/clk/microchip/ |
| D | clk-core.c | 735 struct pic32_sys_pll *spll; in pic32_spll_clk_register() local
738 spll = devm_kzalloc(core->dev, sizeof(*spll), GFP_KERNEL); in pic32_spll_clk_register()
739 if (!spll) in pic32_spll_clk_register()
742 spll->core = core; in pic32_spll_clk_register()
743 spll->hw.init = &data->init_data; in pic32_spll_clk_register()
744 spll->ctrl_reg = data->ctrl_reg + core->iobase; in pic32_spll_clk_register()
745 spll->status_reg = data->status_reg + core->iobase; in pic32_spll_clk_register()
746 spll->lock_mask = data->lock_mask; in pic32_spll_clk_register()
749 spll->idiv = (readl(spll->ctrl_reg) >> PLL_IDIV_SHIFT) & PLL_IDIV_MASK; in pic32_spll_clk_register()
750 spll->idiv += 1; in pic32_spll_clk_register()
[all …]
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| /drivers/gpu/drm/nouveau/nvkm/subdev/clk/ |
| D | nv40.c | 36 u32 spll; member
175 clk->spll = 0xc0000000 | (log2P << 16) | (N1 << 8) | M1; in nv40_clk_calc()
178 clk->spll = 0x00000000; in nv40_clk_calc()
193 nvkm_mask(device, 0x004008, 0xc007ffff, clk->spll); in nv40_clk_prog()
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| D | nv50.c | 474 clk_mask(hwsq, spll[0], 0xc03f0100, (P1 << 19) | (P1 << 16)); in nv50_clk_calc()
481 clk_mask(hwsq, spll[0], 0xc03f0100, in nv50_clk_calc()
483 clk_mask(hwsq, spll[1], 0x0000ffff, (N << 8) | M); in nv50_clk_calc()
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| /drivers/clk/imx/ |
| D | clk-imx31.c | 40 dummy, ckih, ckil, mpll, spll, upll, mcu_main, hsp, ahb, nfc, ipg, enumerator
70 clk[spll] = imx_clk_pllv1(IMX_PLLV1_IMX31, "spll", "ckih", base + MXC_CCM_SRPCTL); in _mx31_clocks_init()
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| /drivers/gpu/drm/i915/display/ |
| D | intel_dpll_mgr.h | 177 u32 spll; member
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| D | intel_dpll_mgr.c | 566 intel_de_write(dev_priv, SPLL_CTL, pll->state.hw_state.spll); in hsw_ddi_spll_enable()
641 hw_state->spll = val; in hsw_ddi_spll_get_hw_state()
997 crtc_state->dpll_hw_state.spll = SPLL_PLL_ENABLE | SPLL_FREQ_1350MHz | in hsw_ddi_spll_get_dpll()
1009 switch (pll->state.hw_state.spll & SPLL_FREQ_MASK) { in hsw_ddi_spll_get_freq()
1072 hw_state->wrpll, hw_state->spll); in hsw_dump_hw_state()
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| /drivers/clk/samsung/ |
| D | clk-exynos5420.c | 150 apll, cpll, dpll, epll, rpll, ipll, spll, vpll, mpll, enumerator
1474 [spll] = PLL(pll_2550, CLK_FOUT_SPLL, "fout_spll", "fin_pll", SPLL_LOCK,
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