| /drivers/net/dsa/ |
| D | vitesse-vsc73xx-platform.c | 42 static u32 vsc73xx_make_addr(u8 block, u8 subblock, u8 reg) in vsc73xx_make_addr() argument
48 ret |= (subblock & VSC73XX_CMD_PLATFORM_SUBBLOCK_MASK) in vsc73xx_make_addr()
55 static int vsc73xx_platform_read(struct vsc73xx *vsc, u8 block, u8 subblock, in vsc73xx_platform_read() argument
61 if (!vsc73xx_is_addr_valid(block, subblock)) in vsc73xx_platform_read()
64 offset = vsc73xx_make_addr(block, subblock, reg); in vsc73xx_platform_read()
73 static int vsc73xx_platform_write(struct vsc73xx *vsc, u8 block, u8 subblock, in vsc73xx_platform_write() argument
79 if (!vsc73xx_is_addr_valid(block, subblock)) in vsc73xx_platform_write()
82 offset = vsc73xx_make_addr(block, subblock, reg); in vsc73xx_platform_write()
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| D | vitesse-vsc73xx-spi.c | 40 static u8 vsc73xx_make_addr(u8 mode, u8 block, u8 subblock) in vsc73xx_make_addr() argument
47 ret |= subblock & VSC73XX_CMD_SPI_SUBBLOCK_MASK; in vsc73xx_make_addr()
52 static int vsc73xx_spi_read(struct vsc73xx *vsc, u8 block, u8 subblock, u8 reg, in vsc73xx_spi_read() argument
62 if (!vsc73xx_is_addr_valid(block, subblock)) in vsc73xx_spi_read()
77 cmd[0] = vsc73xx_make_addr(VSC73XX_CMD_SPI_MODE_READ, block, subblock); in vsc73xx_spi_read()
94 static int vsc73xx_spi_write(struct vsc73xx *vsc, u8 block, u8 subblock, u8 reg, in vsc73xx_spi_write() argument
104 if (!vsc73xx_is_addr_valid(block, subblock)) in vsc73xx_spi_write()
119 cmd[0] = vsc73xx_make_addr(VSC73XX_CMD_SPI_MODE_WRITE, block, subblock); in vsc73xx_spi_write()
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| D | vitesse-vsc73xx.h | 21 int (*read)(struct vsc73xx *vsc, u8 block, u8 subblock, u8 reg,
23 int (*write)(struct vsc73xx *vsc, u8 block, u8 subblock, u8 reg,
27 int vsc73xx_is_addr_valid(u8 block, u8 subblock);
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| D | vitesse-vsc73xx-core.c | 343 int vsc73xx_is_addr_valid(u8 block, u8 subblock) in vsc73xx_is_addr_valid() argument
347 switch (subblock) { in vsc73xx_is_addr_valid()
356 switch (subblock) { in vsc73xx_is_addr_valid()
365 switch (subblock) { in vsc73xx_is_addr_valid()
376 static int vsc73xx_read(struct vsc73xx *vsc, u8 block, u8 subblock, u8 reg, in vsc73xx_read() argument
379 return vsc->ops->read(vsc, block, subblock, reg, val); in vsc73xx_read()
382 static int vsc73xx_write(struct vsc73xx *vsc, u8 block, u8 subblock, u8 reg, in vsc73xx_write() argument
385 return vsc->ops->write(vsc, block, subblock, reg, val); in vsc73xx_write()
388 static int vsc73xx_update_bits(struct vsc73xx *vsc, u8 block, u8 subblock, in vsc73xx_update_bits() argument
395 ret = vsc73xx_read(vsc, block, subblock, reg, &orig); in vsc73xx_update_bits()
[all …]
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| /drivers/spi/ |
| D | spi-fsl-cpm.c | 55 qe_issue_cmd(QE_INIT_TX_RX, mspi->subblock, in fsl_spi_cpm_reinit_txrx()
280 qe_issue_cmd(QE_ASSIGN_PAGE_TO_DEVICE, mspi->subblock, in fsl_spi_cpm_get_pram()
315 mspi->subblock = *iprop; in fsl_spi_cpm_init()
317 switch (mspi->subblock) { in fsl_spi_cpm_init()
322 mspi->subblock = QE_CR_SUBBLOCK_SPI1; in fsl_spi_cpm_init()
325 mspi->subblock = QE_CR_SUBBLOCK_SPI2; in fsl_spi_cpm_init()
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| D | spi-fsl-lib.h | 28 int subblock; member
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| /drivers/gpu/drm/amd/amdgpu/ |
| D | gfx_v9_0.c | 354 #define AMDGPU_RAS_SUB_BLOCK(subblock, a, b, c, d, e, f, g, h) \ argument
355 [AMDGPU_RAS_BLOCK__##subblock] = { \
356 #subblock, \
357 TA_RAS_BLOCK__##subblock, \
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