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Searched refs:swath_height (Results 1 – 13 of 13) sorted by relevance

/drivers/gpu/drm/amd/display/dc/dml/
Ddml1_display_rq_dlg_calc.c132 unsigned int swath_height, in get_vratio_pre() argument
139 vratio_pre = (max_num_sw * swath_height + max_partial_sw) / l_sw; in get_vratio_pre()
141 if (swath_height > 4) { in get_vratio_pre()
142 double tmp0 = (max_num_sw * swath_height) / (l_sw - (prefill - 3.0) / 2.0); in get_vratio_pre()
150 DTRACE("DLG: %s: swath_height = %0d", __func__, swath_height); in get_vratio_pre()
174 unsigned int swath_height, in get_swath_need() argument
180 DTRACE("DLG: %s: swath_height = %0d", __func__, swath_height); in get_swath_need()
185 …*max_num_sw = (unsigned int) (dml_ceil((prefill - 1.0) / (double) swath_height, 1) + 1.0); /* pref… in get_swath_need()
188 (swath_height - 1) : in get_swath_need()
189 ((unsigned int) (prefill - 2.0) % swath_height); in get_swath_need()
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Ddisplay_rq_dlg_helpers.c74 rq_dlg_param.swath_height); in print__data_rq_dlg_params_st()
171 dml_print("DML_RQ_DLG_CALC: swath_height = 0x%0x\n", rq_regs.swath_height); in print__data_rq_regs_st()
Ddisplay_mode_structs.h400 unsigned int swath_height; member
520 unsigned int swath_height; member
/drivers/gpu/drm/amd/display/dc/dcn21/
Ddcn21_hubp.c157 SWATH_HEIGHT, rq_regs->rq_regs_l.swath_height, in hubp21_program_requestor()
165 SWATH_HEIGHT_C, rq_regs->rq_regs_c.swath_height, in hubp21_program_requestor()
279 SWATH_HEIGHT, &rq_regs.rq_regs_l.swath_height, in hubp21_validate_dml_output()
287 SWATH_HEIGHT_C, &rq_regs.rq_regs_c.swath_height, in hubp21_validate_dml_output()
324 if (rq_regs.rq_regs_l.swath_height != dml_rq_regs->rq_regs_l.swath_height) in hubp21_validate_dml_output()
326 dml_rq_regs->rq_regs_l.swath_height, rq_regs.rq_regs_l.swath_height); in hubp21_validate_dml_output()
346 if (rq_regs.rq_regs_c.swath_height != dml_rq_regs->rq_regs_c.swath_height) in hubp21_validate_dml_output()
348 dml_rq_regs->rq_regs_c.swath_height, rq_regs.rq_regs_c.swath_height); in hubp21_validate_dml_output()
/drivers/gpu/drm/amd/display/dc/dcn20/
Ddcn20_hubp.c215 SWATH_HEIGHT, rq_regs->rq_regs_l.swath_height, in hubp2_program_requestor()
224 SWATH_HEIGHT_C, rq_regs->rq_regs_c.swath_height, in hubp2_program_requestor()
1260 SWATH_HEIGHT, &rq_regs->rq_regs_l.swath_height, in hubp2_read_state()
1270 SWATH_HEIGHT_C, &rq_regs->rq_regs_c.swath_height, in hubp2_read_state()
1303 SWATH_HEIGHT, &rq_regs.rq_regs_l.swath_height, in hubp2_validate_dml_output()
1312 SWATH_HEIGHT_C, &rq_regs.rq_regs_c.swath_height, in hubp2_validate_dml_output()
1349 if (rq_regs.rq_regs_l.swath_height != dml_rq_regs->rq_regs_l.swath_height) in hubp2_validate_dml_output()
1351 dml_rq_regs->rq_regs_l.swath_height, rq_regs.rq_regs_l.swath_height); in hubp2_validate_dml_output()
1374 if (rq_regs.rq_regs_c.swath_height != dml_rq_regs->rq_regs_c.swath_height) in hubp2_validate_dml_output()
1376 dml_rq_regs->rq_regs_c.swath_height, rq_regs.rq_regs_c.swath_height); in hubp2_validate_dml_output()
/drivers/gpu/drm/amd/display/dc/dml/dcn20/
Ddisplay_rq_dlg_calc_20.c207 rq_regs->rq_regs_l.swath_height = dml_log2(rq_param.dlg.rq_l.swath_height); in extract_rq_regs()
208 rq_regs->rq_regs_c.swath_height = dml_log2(rq_param.dlg.rq_c.swath_height); in extract_rq_regs()
321 rq_param->dlg.rq_l.swath_height = 1 << log2_swath_height_l; in handle_det_buf_split()
322 rq_param->dlg.rq_c.swath_height = 1 << log2_swath_height_c; in handle_det_buf_split()
Ddisplay_rq_dlg_calc_20v2.c207 rq_regs->rq_regs_l.swath_height = dml_log2(rq_param.dlg.rq_l.swath_height); in extract_rq_regs()
208 rq_regs->rq_regs_c.swath_height = dml_log2(rq_param.dlg.rq_c.swath_height); in extract_rq_regs()
321 rq_param->dlg.rq_l.swath_height = 1 << log2_swath_height_l; in handle_det_buf_split()
322 rq_param->dlg.rq_c.swath_height = 1 << log2_swath_height_c; in handle_det_buf_split()
/drivers/gpu/drm/amd/display/dc/dml/dcn21/
Ddisplay_rq_dlg_calc_21.c187 rq_regs->rq_regs_l.swath_height = dml_log2(rq_param.dlg.rq_l.swath_height); in extract_rq_regs()
188 rq_regs->rq_regs_c.swath_height = dml_log2(rq_param.dlg.rq_c.swath_height); in extract_rq_regs()
305 rq_param->dlg.rq_l.swath_height = 1 << log2_swath_height_l; in handle_det_buf_split()
306 rq_param->dlg.rq_c.swath_height = 1 << log2_swath_height_c; in handle_det_buf_split()
/drivers/gpu/drm/amd/display/dc/dml/dcn30/
Ddisplay_rq_dlg_calc_30.c132 rq_regs->rq_regs_l.swath_height = dml_log2(rq_param.dlg.rq_l.swath_height); in extract_rq_regs()
133 rq_regs->rq_regs_c.swath_height = dml_log2(rq_param.dlg.rq_c.swath_height); in extract_rq_regs()
265 rq_param->dlg.rq_l.swath_height = 1 << log2_swath_height_l; in handle_det_buf_split()
266 rq_param->dlg.rq_c.swath_height = 1 << log2_swath_height_c; in handle_det_buf_split()
/drivers/gpu/drm/amd/display/dc/dcn30/
Ddcn30_hubp.c450 SWATH_HEIGHT, &rq_regs->rq_regs_l.swath_height, in hubp3_read_state()
459 SWATH_HEIGHT_C, &rq_regs->rq_regs_c.swath_height, in hubp3_read_state()
/drivers/gpu/drm/amd/display/dc/dcn10/
Ddcn10_hubp.c572 SWATH_HEIGHT, rq_regs->rq_regs_l.swath_height, in hubp1_program_requestor()
581 SWATH_HEIGHT_C, rq_regs->rq_regs_c.swath_height, in hubp1_program_requestor()
1057 SWATH_HEIGHT, &rq_regs->rq_regs_l.swath_height, in hubp1_read_state()
1067 SWATH_HEIGHT_C, &rq_regs->rq_regs_c.swath_height, in hubp1_read_state()
Ddcn10_hw_sequencer_debug.c216 rq_regs->rq_regs_l.mpte_group_size, rq_regs->rq_regs_l.swath_height, in dcn10_get_rq_states()
220 rq_regs->rq_regs_c.swath_height, rq_regs->rq_regs_c.pte_row_height_linear); in dcn10_get_rq_states()
Ddcn10_hw_sequencer.c206 rq_regs->rq_regs_l.mpte_group_size, rq_regs->rq_regs_l.swath_height, in dcn10_log_hubp_states()
210 rq_regs->rq_regs_c.swath_height, rq_regs->rq_regs_c.pte_row_height_linear); in dcn10_log_hubp_states()